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silego technology, inc. rev 1.06 000-0046121--106 revised october 11, 2017 greenpak dual supply programmable mixed-signal matrix SLG46121 block diagram features ? logic & mixed signal circuits ? highly versatile macrocells ? 1.8 v (5%) to 5 v (10%) vdd ? 1.8 v (5%) to 5 v (1 0%) vdd2 (vdd2 vdd) ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? pb-free 12-pin stqfn: 1.6 x 1.6 x 0.55 mm, 0.4 mm pitch applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics pin configuration gnd gpio gpio gpio gpio gpio 2 3 4 7 8 9 10 gpi vdd 1 stqfn-12 (top view) gpio gpio 5 6 gpio vdd2 11 12 3-bit lut3_1 or dff5 pin 1 vdd pin 2 gpi pin 3 gpio pin 4 gpio pin 12 gpio pin 11 vdd2 pin 5 gpio pin 6 gpio pin 8 gpio pin 7 gnd pin 10 gpio pin 9 gpio acmp0 acmp1 look up tables (luts) counters/delay generators cnt0 cnt1 2-bit lut2_4 3-bit lut3_5 3-bit lut3_4 combination function macrocells 2-bit lut2_0 or dff0 2-bit lut2_1 or dff1 3-bit lut3_0 or dff4 2bit lut2_3 or dff3 2-bit lut2_2 or dff2 3-bit lut3_8 or pipe delay 3-bit lut3_2 or dff6 3-bit lut3_3 or dff7 4-bit lut4_1 or cnt3 4bit lut4_0 or cnt2 3-bit lut2_6 3-bit lut3_7 vref rc oscillator filter_0/prog. delay additional combination functions por bandgap inv_0 additional logic functions
000-0046121--106 page 1 of 97 SLG46121 1.0 overview the SLG46121 provides a small, low power component for commonly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logic, the i/o pins and the macrocells of the SLG46121. this highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power si ngle integrated circuit. the additional power supply (vdd2) on the SLG46121 provides the ability to interface two independent voltage domains within the same design. users can confi gure pins, dedicated to each po wer supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both vdd and vdd2 voltage domains. using the available macrocells designers can implement mixed-signal functions bridging both domains o r simply pass through level-tr anslation in both hig h to low and low to high directions. the macrocells in the device include the following: ? two analog comparators (acmp) ? voltage references (vref) ? five combinatorial look up tables (luts) ? one 2-bit luts ? four 3-bit luts ? twelve combination function macrocell ? four selectable dff/latch or 2-bit luts ? four selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? pipe delay C 8 stage / 2 out put, one 1 stage fixed output ? two selectable counte r/delay or 4-bit lut ? one programmable delay / deglitch filter ? two counter / delay generators (cnt/dly) ? one 8-bit counter/delay ? one 14-bit counter/delay w ith external clock/reset ? eight d flip-flop / latches (dff) (part of combination functio n macrocell) ? additional logic function - 1 inverter ? pipe delay C 8 stage/2 output ( part of combination function ma crocell) ? one bandgap ? rc oscillator (rc osc) ? power on reset (por)
000-0046121--106 page 2 of 97 SLG46121 2.0 pin description 2.1 functional pin description pin # pin name function 1 vdd power supply (pin 2, 3, 4, 5, 6) 2 gpi general purpose input 3 gpio general purpose i/o o r analog comparator 0 (+) 4 gpio general purpose i/o o r analog comparator 0 (-) 5 gpio general purpose i/o 6 gpio general purpose i/o or an alog comparator 1 (+) with oe 7 gnd ground 8 gpio general purpose i/o 9 gpio general purpose i/o 10 gpio general purpose i/o with oe and v ref output 11 vdd2 power supply (pin 8, 9, 10, 12) 12 gpio general purpose i/o or external clock input
000-0046121--106 page 3 of 97 SLG46121 3.0 user programmability non-volatile memory (nvm) is used to configure the SLG46121s c onnection matrix routing and macrocells. the nvm is one-time-programmable (otp). how ever, silegos greenpak develop ment tools can be used to configure the connection matrix and macrocells, without programming the nvm, to allow on-chip e mulation. this configuration will remain active on the device a s long as it remains powered and c an be re-written as needed to f acilitate rapid design changes. when a design is ready for in-circuit testing, the same greenpa k development tools can be used to program the nvm and create samples for small quantity builds. once the nvm is programmed, the device will retain this conf iguration for the duration of i ts lifetime. once the design is finalized, the design file c an be forwarded to silego to integ rate into the produ ction process. figure 1. steps to create a cu stom silego greenpak device product definition customer creates their own design in greenpak designer program engineering samples with greenpak development tools customer verifies greenpak in system design e-mail design file to greenpak@silego.com e-mail product idea, definition, drawing, or schematic to greenpak@silego.com silego applications engineers will review design specifications with customer samples and design & characterization report sent to customer customer verifies greenpak design custom greenpak part enters production greenpak design approved in system test greenpak design approved greenpak design approved emulate design to verify behavior
000-0046121--106 page 4 of 97 SLG46121 4.0 ordering information part number type SLG46121v 12-pin stqfn SLG46121vtr 12-pin stqfn - tape and reel (3k units)
000-0046121--106 page 5 of 97 SLG46121 5.0 electrical specifications 5.1 absolute maximum conditions 5.2 electrical charac teristics (1.8v 5% v dd ) parameter min. max. unit supply voltage on vdd re lative to gnd -0.5 7 v supply voltage on vdd2 relative to gnd -0.5 vdd + 0.5 v dc input voltage pins 2,3,4,5,6 gnd - 0.5 vdd + 0.5 v pins 8,9,10,12 vdd2 + 0.5 maximum average or dc current (through pin) push-pull 1x -- 12 ma push-pull 2x -- 17 od 1x -- 18 od 2x -- 28 current at input pin -1.0 1.0 ma storage temperature range -65 150 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 500 -- v moisture sensitivity level 1 symbol parameter condition/note min. typ. max. unit v dd supply voltage vdd2 vdd 1.71 1.80 1.89 v i q quiescent current static inputs and outputs (when acmp, vref and rc osc are powered down and non-operational) -- 0.5 -- ? a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd negative input 0 -- 1.1 v ih high-level input voltage pin 2, 3, 4, 5, 6 logic input 1.100 -- v dd v logic input with schm itt trigger 1.270 -- v dd v low-level logic input 0.980 -- v dd v v il low-level input voltage pin 2, 3, 4, 5, 6 logic input -- -- 0.690 v logic input with schm itt trigger -- -- 0.440 v low-level logic input -- -- 0.520 v v hys schmitt trigger hysteresis voltage logic input with schmitt trigger 0.280 0.445 0.600 v i lgk input leakage pin 2, 3, 4, 5, 6 (absolute value) -- 1 1000 na v oh high-level output voltage pin 2, 3, 4, 5, 6 push-pull 1x, open drain pmos 1x, i oh = 100 ? a 1.680 1.790 -- v push-pull 2x, open drain pmos 2x, i oh = 100 ? a 1.700 1.800 -- v
000-0046121--106 page 6 of 97 SLG46121 v ol low-level output voltage pin 2, 3, 4, 5, 6 push-pull 1x, i ol = 100 ? a -- 0.020 0.030 v push-pull 2x, i ol = 100 ? a -- 0.010 0.020 v open drain nmos 1x, i ol = 100 ? a -- 0.010 0.020 v open drain nmos 2x, i ol = 100 ? a -- 0.010 0.010 v i oh high-level output current (see note 1) pin 2, 3, 4, 5, 6 push-pull 1x, open drain pmos 1x, v oh = v dd - 0.2 1.000 1.390 -- ma push-pull 2x, open drain pmos 2x, v oh = v dd - 0.2 2.100 2.680 -- ma i ol low-level output current (see note 1) pin 2, 3, 4, 5, 6 push-pull 1x, v ol = 0.15 v 0.760 1.340 -- ma push-pull 2x, v ol = 0.15 v 1.520 2.660 -- ma open drain nmos 1x, v ol = 0.15 v 1.530 2.670 -- ma open drain nmos 2x, v ol = 0.15 v 3.060 5.136 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma t su startup time from vdd rising past 1.35 v -- 0.31 -- ms pon thr power on threshold v dd level required to start up the chip 1.180 1.353 1.516 v poff thr power off threshold v dd level required to switch off the chip 0.730 0.914 1.103 v r pup pull up resistance 1 m pull up 975.92 1061.05 1132.72 k ? 100 k pull up 99.56 107.15 114.11 k ? 10 k pull up 11.51 12.86 14.36 k ? r pdwn pull down resistance 1 m pull down 975.32 1061.05 1133.17 k ? 100 k pull down 100.43 107.26 114.05 k ? 10 k pull down 11.17 12.48 13.86 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. symbol parameter condition/note min. typ. max. unit
000-0046121--106 page 7 of 97 SLG46121 5.3 electrical charac teristics (3.3v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v i q quiescent current static inputs and outputs (when acmp, vref and rc osc are powered down and non-operational) -- 0.75 -- ? a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level input voltage pin 2, 3, 4, 5, 6 logic input 1.780 -- v dd v logic input with schm itt trigger 2.130 -- v dd v low-level logic input 1.130 -- v dd v v il low-level input voltage pin 2, 3, 4, 5, 6 logic input -- -- 1.210 v logic input with schm itt trigger -- -- 0.950 v low-level logic input -- -- 0.690 v v hys schmitt trigger hysteresis voltage logic input with schmitt trigger 0.498 0.685 0.866 v i lgk input leakage pin 2, 3, 4, 5, 6 (absolute value) -- 1 1000 na v oh high-level output voltage pin 2, 3, 4, 5, 6 push-pull 1x,open drain pmos 1x, i oh = 3 ma 2.720 3.090 -- v push-pull 2x, open drain pmos 2x, i oh = 3 ma 2.850 3.190 -- v v ol low-level output voltage pin 2, 3, 4, 5, 6 push-pull 1x, i ol = 3 ma -- 0.180 0.280 v push-pull 2x, i ol = 3 ma -- 0.090 0.130 v open drain nmos 1x, i ol = 3 ma -- 0.090 0.130 v open drain nmos 2x, i ol = 3 ma -- 0.050 0.070 v i oh high-level output current (see note 1) pin 2, 3, 4, 5, 6 push-pull 1x, open drain pmos 1x, v oh = 2.4 v 6.010 10.150 -- ma push-pull 2x, open drain pmos 2x, v oh = 2.4 v 11.460 19.610 -- ma i ol low-level output current (see note 1) pin 2, 3, 4, 5, 6 push-pull 1x, v ol = 0.4 v 4.060 6.440 -- ma push-pull 2x, v ol = 0.4 v 8.130 12.360 -- ma open drain nmos 1x, v ol = 0.4 v 8.130 12.410 -- ma open drain nmos 2x, v ol = 0.4 v 16.260 22.900 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma
000-0046121--106 page 8 of 97 SLG46121 5.4 electrical charac teristics (5v 10% v dd ) i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma t su startup time from vdd rising past 1.35 v -- 0.31 -- ms pon thr power on threshold v dd level required to start up the chip 1.180 1.353 1.516 v poff thr power off threshold v dd level required to switch off the chip 0.730 0.914 1.103 v r pup pull up resistance 1 m pull up 976.93 1060.60 1140.64 k ? 100 k pull up 98.50 106.38 113.21 k ? 10 k pull up 10.22 11.66 12.95 k ? r pdwn pull down resistance 1 m pull down 974.63 1060.65 1132.96 k ? 100 k pull down 99.69 106.50 113.26 k ? 10 k pull down 9.94 11.46 12.85 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. symbol parameter condition/note min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v i q quiescent current static inputs and outputs (when acmp, vref and rc osc are powered down and non-operational) -- 1.0 -- ? a t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level input voltage pin 2, 3, 4, 5, 6 logic input 2.640 -- v dd v logic input with schm itt trigger 3.160 -- v dd v low-level logic input 1.230 -- v dd v v il low-level input voltage pin 2, 3, 4, 5, 6 logic input -- -- 1.840 v logic input with schmitt trigger -- -- 1.510 v low-level logic input -- -- 0.780 v v hys schmitt trigger hysteresis voltage logic input with schmit t trigger 0.694 0.923 1.182 v i lgk input leakage pin 2, 3, 4, 5, 6 (absolute value) -- 1 1000 na v oh high-level output voltage pin 2, 3, 4, 5, 6 push-pull 1x,open drain pmos 1x, i oh = 5 ma 4.170 4.740 -- v push-pull 2x, open drain pmos 2x, i oh = 5 ma 4.320 4.860 -- v symbol parameter condition/note min. typ. max. unit
000-0046121--106 page 9 of 97 SLG46121 v ol low-level output voltage pin 2, 3, 4, 5, 6 push-pull 1x, i ol = 5 ma -- 0.230 0.330 v push-pull 2x, i ol = 5 ma -- 0.120 0.160 v open drain nmos 1x, i ol = 5 ma -- 0.120 0.160 v open drain nmos 2x, i ol = 5 ma -- 0.700 0.090 v i oh high-level output current (see note 1) pin 2, 3, 4, 5, 6 push-pull 1x, open drain pmos 1x, v oh = 2.4 v 21.980 29.0010 -- ma push-pull 2x, open drain pmos 2x, v oh = 2.4 v 41.886 55.990 -- ma i ol low-level output current (see note 1) pin 2, 3, 4, 5, 6 push-pull 1x, v ol = 0.4 v 6.010 9.730 -- ma push-pull 2x, v ol = 0.4 v 11.590 19.460 -- ma open drain nmos 1x, v ol = 0.4 v 11.760 19.460 -- ma open drain nmos 2x, v ol = 0.4 v 19.120 35.952 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma t su startup time from vdd rising past 1.35 v -- 0.31 -- ms pon thr power on threshold v dd level required to start up the chip 1.180 1.353 1.516 v poff thr power off threshold v dd level required to switch off the chip 0.730 0.914 1.103 v r pup pull up resistance 1 m pull up 972.75 1060.76 1134.23 k ? 100 k pull up 98.89 106.16 112.84 k ? 10 k pull up 9.27 11.11 12.62 k ? r pdwn pull down resistance 1 m pull down 968.47 1060.59 1138.02 k ? 100 k pull down 99.49 106.23 113.02 k ? 10 k pull down 9.06 10.97 12.57 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. symbol parameter condition/note min. typ. max. unit
000-0046121--106 page 10 of 97 SLG46121 5.5 electrical charac teristics (1.8v 5% v dd2 ) symbol parameter condition/note min. typ. max. unit v dd2 supply voltage vdd2 vdd 1.71 1.80 1.89 v i lgk input leakage pi n 8, 9, 10, 12 (absolute value) -- 1 1000 na v ih2 high-level input voltage pin 8, 9, 10, 12 logic input 1.100 -- v dd2 v logic input with schm itt trigger 1.270 -- v dd2 v low-level logic input 0.980 -- v dd2 v v il2 low-level input voltage pin 8, 9, 10, 12 logic input -- -- 0.690 v logic input with schm itt trigger -- -- 0.440 v low-level logic input -- -- 0.520 v v oh2 high-level output voltage pin 8, 9, 10, 12 push-pull 1x, open drain pmos 1x, i oh = 100 ? a 1.680 1.790 -- v push-pull 2x, open drain pmos 2x, i oh = 100 ? a 1.700 1.800 -- v v ol2 low-level output voltage pin 8, 9, 10, 12 push-pull 1x, i ol = 100 ? a -- 0.020 0.030 v push-pull 2x, i ol = 100 ? a -- 0.010 0.020 v open drain nmos 1x, i ol = 100 ? a -- 0.010 0.020 v open drain nmos 2x, i ol = 100 ? a -- 0.010 0.010 v i oh2 high-level output current (see note 1) pin 8, 9, 10, 12 push-pull 1x, open drain pmos 1x, v oh = v dd - 0.2 1.000 1.390 -- ma push-pull 2x, open drain pmos 2x, v oh = v dd - 0.2 2.100 2.680 -- ma i ol2 low-level output current (see note 1) pin 8, 9, 10, 12 push-pull 1x, v ol = 0.15 v 0.760 1.340 -- ma push-pull 2x, v ol = 0.15 v 1.520 2.660 -- ma open drain nmos 1x, v ol = 0.15 v 1.530 2.670 -- ma open drain nmos 2x, v ol = 0.15 v 3.060 5.136 -- ma i vdd2 maximum average or dc current through vdd2 pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another.
000-0046121--106 page 11 of 97 SLG46121 5.6 electrical charac teristics (3.3v 10% v dd2 ) symbol parameter condition/note min. typ. max. unit v dd2 supply voltage vdd2 vdd 1.71 -- v dd2 v i lgk input leakage pi n 8, 9, 10, 12 (absolute value) -- 1 1000 na v ih2 high-level input voltage pin 8, 9, 10, 12 logic input, v dd2 = 1.8 v 1.100 -- v dd2 v logic input with schmitt trigger, v dd2 = 1.8 v 1.270 -- v dd2 v low-level logic input, v dd2 = 1.8 v 0.980 -- v dd2 v v il2 low-level input voltage pin 8, 9, 10, 12 logic input, v dd2 = 1.8 v -- -- 0.690 v logic input with schmitt trigger, v dd2 = 1.8 v -- -- 0.440 v low-level logic input, v dd2 = 1.8 v -- -- 0.520 v v oh2 high-level output voltage pin 8, 9, 10, 12 push-pull 1x, open drain pmos 1x, i oh = 100 ? a, v dd2 = 1.8 v 1.680 1.790 -- v push-pull 2x, open drain pmos 2x, i oh = 100 ? a, v dd2 = 1.8 v 1.700 1.800 -- v v ol2 low-level output voltage pin 8, 9, 10, 12 push-pull 1x, i ol = 100 ? a, v dd2 = 1.8 v -- 0.020 0.030 v push-pull 2x, i ol = 100 ? a, v dd2 = 1.8 v -- 0.010 0.020 v open drain nmos 1x, i ol = 100 ? a, v dd2 = 1.8 v -- 0.010 0.020 v open drain nmos 2x, i ol = 100 ? a, v dd2 = 1.8 v -- 0.010 0.010 v i oh2 high-level output current (see note 1) pin 8, 9, 10, 12 push-pull 1x, open drain pmos 1x, v oh = v dd - 0.2, v dd2 = 1.8 v 1.000 1.390 -- ma push-pull 2x, open drain pmos 2x, v oh = v dd - 0.2, v dd2 = 1.8 v 2.100 2.680 -- ma i ol2 low-level output current (see note 1) pin 8, 9, 10, 12 push-pull 1x, v ol = 0.15 v, v dd2 = 1.8 v 0.760 1.340 -- ma push-pull 2x, v ol = 0.15 v, v dd2 = 1.8 v 1.520 2.660 -- ma open drain nmos 1x, v ol = 0.15 v, v dd2 = 1.8 v 1.530 2.670 -- ma open drain nmos 2x, v ol = 0.15 v, v dd2 = 1.8 v 3.060 5.136 -- ma i vdd2 maximum average or dc current through vdd2 pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another.
000-0046121--106 page 12 of 97 SLG46121 5.7 electrical charac teristics (5v 10% v dd2 ) symbol parameter condition/note min. typ. max. unit v dd2 supply voltage vdd2 vdd 1.71 -- v dd2 v i lgk input leakage pi n 8, 9, 10, 12 (absolute value) -- 1 1000 na v ih2 high-level input voltage pin 8, 9, 10, 12 logic input, v dd2 = 3.3 v 1.780 -- v dd2 v logic input with schmitt trigger, v dd2 = 3.3 v 2.130 -- v dd2 v low-level logic input, v dd2 = 3.3 v 1.130 -- v dd2 v v il2 low-level input voltage pin 8, 9, 10, 12 logic input, v dd2 = 3.3 v -- -- 1.210 v logic input with schmitt trigger, v dd2 = 3.3 v -- -- 0.950 v low-level logic input, v dd2 = 3.3 v -- -- 0.690 v v oh2 high-level output voltage pin 8, 9, 10, 12 push-pull 1x,open drain pmos 1x, i oh = 3 ma, v dd2 = 3.3 v 2.720 3.090 -- v push-pull 2x, open drain pmos 2x, i oh = 3 ma, v dd2 = 3.3 v 2.850 3.190 -- v v ol2 low-level output voltage pin 8, 9, 10, 12 push-pull 1x, i ol = 3 ma, v dd2 = 3.3 v -- 0.180 0.280 v push-pull 2x, i ol = 3 ma, v dd2 = 3.3 v -- 0.090 0.130 v open drain nmos 1x, i ol = 3 ma, v dd2 = 3.3 v -- 0.090 0.130 v open drain nmos 2x, i ol = 3 ma, v dd2 = 3.3 v -- 0.050 0.070 v i oh2 high-level output current (see note 1) pin 8, 9, 10, 12 push-pull 1x, open drain pmos 1x, v oh = 2.4 v, v dd2 = 3.3 v 6.010 10.150 -- ma push-pull 2x, open drain pmos 2x, v oh = 2.4 v, v dd2 = 3.3 v 11.460 19.610 -- ma i ol2 low-level output current (see note 1) pin 8, 9, 10, 12 push-pull 1x, v ol = 0.4 v, v dd2 = 3.3 v 4.060 6.440 -- ma push-pull 2x, v ol = 0.4 v, v dd2 = 3.3 v 8.130 12.360 -- ma open drain nmos 1x, v ol = 0.4 v, v dd2 = 3.3 v 8.130 12.410 -- ma open drain nmos 2x, v ol = 0.4 v, v dd2 = 3.3 v 16.260 22.900 -- ma v ih2 high-level input voltage pin 8, 9, 10, 12 logic input, v dd2 = 1.8 v 1.100 -- v dd v logic input with schmitt trigger, v dd2 = 1.8 v 1.270 -- v dd v low-level logic input, v dd2 = 1.8 v 0.980 -- v dd v v il2 low-level input voltage pin 8, 9, 10, 12 logic input, v dd2 = 1.8 v -- -- 0.690 v logic input with schmitt trigger, v dd2 = 1.8 v -- -- 0.440 v low-level logic input, v dd2 = 1.8 v -- -- 0.520 v i ih2 high-level input current pin 8, 9, 10, 12 logic input pins; v in = 1.8 v, v dd2 = 1.8 v -1.0 -- 1.0 ? a
000-0046121--106 page 13 of 97 SLG46121 i il2 low-level input current pin 8, 9, 10, 12 logic input pins; v in = 0 v, v dd2 = 1.8 v -1.0 -- 1.0 ? a v oh2 high-level output voltage pin 8, 9, 10, 12 push-pull 1x, open drain pmos 1x, i oh = 100 ? a, v dd2 = 1.8 v 1.680 1.790 -- v push-pull 2x, open drain pmos 2x, i oh = 100 ? a, v dd2 = 1.8 v 1.700 1.800 -- v v ol2 low-level output voltage pin 8, 9, 10, 12 push-pull 1x, i ol = 100 ? a, v dd2 = 1.8 v -- 0.020 0.030 v push-pull 2x, i ol = 100 ? a, v dd2 = 1.8 v -- 0.010 0.020 v open drain nmos 1x, i ol = 100 ? a, v dd2 = 1.8 v -- 0.010 0.020 v open drain nmos 2x, i ol = 100 ? a, v dd2 = 1.8 v -- 0.010 0.010 v i oh2 high-level output current (see note 1) pin 8, 9, 10, 12 push-pull 1x, open drain pmos 1x, v oh = v dd - 0.2, v dd2 = 1.8 v 1.000 1.390 -- ma push-pull 2x, open drain pmos 2x, v oh = v dd - 0.2, v dd2 = 1.8 v 2.100 2.680 -- ma i ol2 low-level output current (see note 1) pin 8, 9, 10, 12 push-pull 1x, v ol = 0.15 v, v dd2 = 1.8 v 0.760 1.340 -- ma push-pull 2x, v ol = 0.15 v, v dd2 = 1.8 v 1.520 2.660 -- ma open drain nmos 1x, v ol = 0.15 v, v dd2 = 1.8 v 1.530 2.670 -- ma open drain nmos 2x, v ol = 0.15 v, v dd2 = 1.8 v 3.060 5.136 -- ma i vdd2 maximum average or dc current through vdd2 pin (per chip side, see note 2) t j = 85c -- -- 73 ma t j = 110c -- -- 35 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 92 ma t j = 110c -- -- 44 ma note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5 and 6 are connected to one side, pins 8, 9, 10 and 12 to another. symbol parameter condition/note min. typ. max. unit
000-0046121--106 page 14 of 97 SLG46121 5.8 idd estimator 5.9 timing estimator table 1. typical current est imated for each macrocell. symbol parameter note v dd = 1.8v v dd = 3.3v v dd = 5.0v unit i current chip quiescent 0.5 0.8 1.0 ? a vref 55.7 56.0 62.5 ? a vref buffer (each) 0.6 14.1 14.6 ? a osc 25 khz, predivide = 1 3.1 4.7 6.4 ? a osc 25 khz, predivide = 8 3.0 4.3 5.8 ? a osc 2 mhz, predivide = 1 29.3 51.0 79.8 ? a osc 2 mhz, predivide = 8 17.4 23.2 29.0 ? a 1st acmp used (includes vref) 59.6 60.0 66.5 ? a each additional acmp add 3.9 4.0 4.0 ? a table 2. typical delay estimated for each macrocell. symbol parameter note v dd /v dd2 = 1.8v v dd /v dd2 = 3.3v v dd /v dd2 = 5.0v unit rising falling rising falling rising falling tpd delay digital input without schmitt trigger -- push pull 44.2 43.5 17.8 18.2 12.7 13.0 ns tpd delay digital input with schmitt trigger -- push pull 43.3 42.5 17.7 18.0 12.6 13.0 ns tpd delay low voltage digital inpu t -- push pull 45.6 517.0 18.1 215 .3 12.7 144.9 ns tpd delay digital input without schmitt trigger -- nmos 83.8 29.9 19.5 ns tpd delay output enable from pin , oe hi-z to 1 44.8 17.9 12.6 ns tpd delay output enable from pin , oe hi-z to 0 43.4 17.7 12.8 ns tpd delay 2-bit lut 18.7 22.1 8.0 8.7 5.8 6.0 ns tpd delay latch (2-bit lut shared macrocell inputs) 26.5 30.8 11.3 12.3 8.1 8.5 ns tpd delay 3-bit lut 21.3 24.4 9.1 9.6 6.5 6.6 ns tpd delay 3-bit lut (latch shared macrocell inputs) 26.8 25.4 11.2 10.2 8.0 7.1 ns tpd delay latch with nrst/nset (3-bit lut shared macrocell inputs) 29.7 34.7 12.6 13.9 9.1 9.6 ns tpd delay 4-bit lut (shared macroc ell inputs) 34.0 32.6 14.4 13.0 10.3 9.1 ns tpd delay 2-bit lut (latch shared macrocell inputs) 26.8 25.4 11.2 10.2 8.0 7.1 ns tpd delay cnt/dly 44.2 38.8 18.7 16.4 13.3 11.8 ns tpd delay cnt/dly (shared macroce ll inputs) 43.2 39.7 18.4 16.8 13.0 12 .1 ns tpd delay cnt3/dly3 rising edge detect (shared macrocell inputs) 38.2 16.0 11.4 ns tpd delay cnt3/dly3 falling edge detect (shared macrocell inputs) 40.4 16.4 11.6 ns tpd delay cnt3/dly3 both edge detect (shared macrocell inputs) 38.2 40.5 15.9 16.5 11.3 11.5 ns tpd delay filter 191.6 193 77.4 77.8 50.7 52.1 ns
000-0046121--106 page 15 of 97 SLG46121 5.10 typical counter/de lay offset measurements 5.11 expected delays and widths table 3. typical counter/de lay offset measurements. parameter rc osc freq rc osc power v dd = 1.8v v dd = 3.3v v dd = 5.0v unit offset 25 khz auto 19 14 12 ? s offset 2 mhz auto 7 4 4 ? s frequency settling time 25 khz auto 19 14 12 ? s frequency settling time 2 mhz auto 14 14 14 ? s variable (clk period) 25 khz forced 0-40 0-40 0-40 ? s variable (clk period) 2 mhz forced 0-0.5 0-0.5 0-0.5 ? s tpd (non-delayed edge) 25 khz/ 2 mhz either 35 14 10 ns table 4. expected delays and wid ths for programmable delay (typi cal). symbol parameter note v dd /v dd2 = 1.8v v dd /v dd2 = 3.3v v dd /v dd2 = 5.0v unit time1 width, 1 cell pdly mode:(any)edge detect, edge detect output 256.7 120.8 110 ns time1 width, 2 cell pdly mode:(any)edge detect, edge detect output 564.4 262.7 225 ns time1 width, 3 cell pdly mode:(any)edge detect, edge detect output 873.5 405 340 ns time1 width, 4 cell pdly mode:(any)edge detect, edge detect output 11.82.3 547.5 450 ns time2 delay, 1 cell pdly mode:(any)edge detect, edge detect output 48.2 20 14 ns time2 delay, 2 cell pdly mode:(any)edge detect, edge detect output 48.2 20.1 14 ns time2 delay, 3 cell pdly mode:(any)edge detect, edge detect output 48.2 20.1 14 ns time2 delay, 4 cell pdly mode:(any)edge detect, edge detect output 48.3 20.1 14 ns time1 delay, 1 cell pdly mode: both edge delay (shared macrocell inputs) 357.9 162.2 110 ns time1 delay, 2 cell pdly mode: both edge delay (shared macrocell inputs) 666.1 304.3 220 ns time1 delay, 3 cell pdly mode: both edge delay (shared macrocell inputs) 974.7 446.3 335 ns time1 delay, 4 cell pdly mode: both edge delay (shared macrocell inputs) 1283.8 588.8 450 ns time1 width cnt3/dly3 rising edge detect (shared macrocell inputs) 136.6 73.4 140 ns time1 width cnt3/dly3 falling edge detect (shared macrocell inputs) 130.6 71 140 ns time1 width cnt3/dly3 both edge detect (shared macrocell inputs) 133.05 72 140 ns
000-0046121--106 page 16 of 97 SLG46121 5.12 typical pulse width performance table 5. typical pulse width performance. parameter v dd /v dd2 = 1.8v v dd /v dd2 = 3.3v v dd /v dd2 = 5.0v unit filtered pulse width < 150 < 55 < 35 ns
000-0046121--106 page 17 of 97 SLG46121 6.0 summary of macrocell function 6.1 i/o pins ? digital input (low voltage or normal voltage, with or without schmitt trigger) ? open drain nmos and o pen drain pm os outputs ? push pull outputs ? analog i/o ? 10 k ? /100 k ? /1 m ?? pull-up/pull-down resistors 6.2 connection matrix ? digital matrix for circuit co nnections based on user design 6.3 analog compa rators (2 total) ? selectable hysteresis 0 mv/25 m v/50 mv/200 mv an d selectable g ain 1x/0.5x/0.33x/0.25x 6.4 voltage reference ? used for references on analog comparators ? can also be driven to external pins 6.5 combinational logic look up tables (luts C 5 total) ? one 2-bit lookup tables ? four 3-bit lookup tables 6.6 combination function macrocells (12 total) ? four selectable dff/latches or 2-bit luts ? four selectable dff/latches or 3-bit luts ? one selectable pipe delay or 3-bit lut ? two selectable cnt/dlys or 4-bit luts ? one programmable delay or deglitch filter 6.7 delays/counters (2 total) ? one 8-bit delay/counter with ex ternal clock/reset: range 1-255 clock cycles ? one 14-bit delay/co unter with external c lock: range 1-16383 cl ock cycles 6.8 pipe delay (part of combination function macrocell) ? 8 stage / 2 output ? two 1-8 stage sel ectable outputs ? one 1 stage fixed output 6.9 additional logic functions (part of combination function macrocell) ? one deglitch filter macrocell ? one programmable delay ? 163 ns / 305 ns / 446 ns / 588 ns @ 3.3 v ? includes edge detection function
000-0046121--106 page 18 of 97 SLG46121 6.10 additional logic function ? one inverter 6.11 rc oscillator ? 25 khz and 2 mhz s electable frequency ? first stage clock pre=divider (4) : osc/1, osc/2, osc/4, and os c/8 ? second stage divider control wit h two outputs, out0 and out1 ( 8): selectable (osc/1, osc /2, osc/3, osc/4, osc/8, osc/12, osc/24, or osc/64) 6.12 power on reset (por)
000-0046121--106 page 19 of 97 SLG46121 7.0 i/o pins the SLG46121 has a total of 9 multi-function i/o pins which can function as either a user defined input or output, as well as serving as a special function (su ch as outputting the voltage r eference). refer to section 2.0 p in description for pin definit ions. all of the 9 user defined i/o pin s on the SLG46121, exept pin 2 can serve as both digital inpu t and digital output. pin 2 can only serve as a digital input pin. the high side of the user selectable push-pull or open-drain pi n output structures for each gpio is connected to either vdd or vdd2. this allows for the appropriate voltage level output comp atible with each voltage domain. the level shifters are located in lower power io pads (pins 8, 9 , 10 and 12) powered from vdd2. a ll configuration r egisters of the slg 46121 are powered from vdd, so it is possible to maintai n the configuration informatio n even after vdd2 was turned off, discharged and turned back on again. 7.1 input modes each i/o pin can be configured as a digital input pin with/with out buffered schmitt trigger, or can also be configured as a lo w voltage digital input. pins 3, 4, and 6 can als o be configured to serve as analog inputs to the on-chip comparators. 7.2 output modes pins 3, 4, 5, 6, 8, 9, 10, and 12 can all be configured as digi tal output pins. 7.3 pull up/down resistors all i/o pins have the option for user selectable resistors conn ected to the input structure. th e selectable values on these re sistors are 10 k ? , 100 k ? and 1 m ? . in the case of pin 2, the resistors are fixed to a pull-down configuration. in the case of all other i/o pins, the internal resistors can be configured as either pull-u p or pull-downs.
000-0046121--106 page 20 of 97 SLG46121 7.4 i/o register settings 7.4.1 pin 2 re gister settings 7.4.2 pin 3 re gister settings table 6. pin 2 re gister settings signal function register bit address register definition pin 2 mode control reg <624:623> 00 : digital input without schmit t trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved pin 2 pull down resistor value selection reg <626:625> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor table 7. pin 3 re gister settings signal function register bit address register definition pin 3 mode control reg <629:627> 0 00: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain nmos pin 3 pull up/down resistor value selection reg <631:630> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 3 pull up/down resistor selection reg <632> 0: pull down resistor 1: pull up resistor pin3 driver strength selection reg <633> 0: 1x 1: 2x
000-0046121--106 page 21 of 97 SLG46121 7.4.3 pin 4 re gister settings 7.4.4 pin 5 re gister settings table 8. pin 4 re gister settings signal function register bit address register definition pin 4 mode control reg <636:634> 0 00: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain nmos pin 4 pull up/down resistor value selection reg <638:637> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 4 pull up/down resistor selection reg <639> 0: pull down resistor 1: pull up resistor pin 4 driver strength selection reg <640> 0: 1x 1: 2x table 9. pin 5 re gister settings signal function register bit address register definition pin 5 mode control reg <643:641> 0 00: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved & open drain nmos pin 5 pull up/down resistor value selection reg <645:644> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 5 pull up/down resistor selection reg <646> 0: pull down resistor 1: pull up resistor pin 5 driver strength selection reg <647> 0: 1x 1: 2x
000-0046121--106 page 22 of 97 SLG46121 7.4.5 pin 6 re gister settings 7.5 pin 8 register settings table 10. pin 6 register settings signal function register bit address register definition pin 6 mode control (sig_pin6_oe =0) reg <649:648> 00: digital i nput without sc hmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input / output pin 6 mode control (sig_pin6_oe =1) reg <651:650> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x pin 6 pull up/down resistor value selection reg <653:652> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 6 pull up/down resistor selection reg <654> 0: pull down resistor 1: pull up resistor table 11. pin 8 register settings signal function register bit address register definition pin 8 mode control reg <657:655> 0 00: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos pin 8 pull up/down resistor value selection reg <659:658> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 8 pull up/down resistor selection reg <660> 0: pull down resistor 1: pull up resistor pin 8 driver strength selection reg <661> 0: 1x 1: 2x
000-0046121--106 page 23 of 97 SLG46121 7.5.1 pin 9 re gister settings 7.6 pin 10 register settings table 12. pin 9 register settings signal function register bit address register definition pin 9 mode control reg <664:662> 0 00: digital input without schmi tt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos pin 9 pull up/down resistor value selection reg <666:665> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 9 pull up/down resistor selection reg <667> 0: pull down resistor 1: pull up resistor pin 8 driver strength selection reg <668> 0: 1x 1: 2x table 13. pin 10 register settings signal function register bit address register definition pin 10 mode control (sig_pin10_oe =0) reg <670:669> 00: digital i nput without sc hmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input pin 10 mode control (sig_pin10_oe =1) reg <672:671> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x pin 10 pull up/down resistor value selection reg <674:673> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 10 pull up/down resistor selection reg <675> 0: pull down resistor 1: pull up resistor
000-0046121--106 page 24 of 97 SLG46121 7.7 pin 12 register settings table 14. pin 12 register settings signal function register bit address register definition pin 12 mode control reg <685:683> 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain nmos 111: open drain nmos pin 12 pull up/down resistor value selection reg <687:686> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 12 pull up/down resistor selection reg <688> 0: pull down resistor 1: pull up resistor pin 12 driver strength selection reg <689> 0: 1x 1: 2x
000-0046121--106 page 25 of 97 SLG46121 7.8 gpi io structure 7.8.1 gpi io structure (for pin 2) figure 2. pin 2 gpi io structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schmitt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode analog io vdd
000-0046121--106 page 26 of 97 SLG46121 7.9 matrix oe io structure 7.9.1 matrix oe io str ucture (for pin 6) figure 3. matrix oe io structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schm itt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1 analog io digital out digital out oe od2x_en oe od1x_en digital out oe pp2x_en digital out oe pp1x_en vdd vdd vdd
000-0046121--106 page 27 of 97 SLG46121 7.9.2 matrix oe io str ucture (fo r pin 10) figure 4. matrix oe io structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schm itt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1 analog io digital out digital out oe od2x_en oe od1x_en digital out oe pp2x_en digital out oe pp1x_en vdd2 vdd2 vdd2
000-0046121--106 page 28 of 97 SLG46121 7.10 register oe io structure 7.10.1 register oe io structure (for pins 3, 4, 5) figure 5. register oe io structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1 001: digital in with schmitt trigger, smt_en=1 010: low voltage digital in mode, lv_en = 1 011: analog io mode 100: push-pull mode, pp_en=1 101: nmos open drain mode, odn_en=1 110: pmos open drain mode, odp_en=1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 analog io digital out digital out oe odn_en oe odn_en digital out oe 2x_en pp_en 2x_en odp_en digital out oe pp_en odp_en vdd vdd vdd
000-0046121--106 page 29 of 97 SLG46121 7.10.2 register oe io st ructure (for pins 8, 9, 12) figure 6. register oe io structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? wosmt_en smt_en lv_en low voltage input schmitt trigger input non-schmitt trigger input mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1 001: digital in with schmitt trigger, smt_en=1 010: low voltage digital in mode, lv_en = 1 011: analog io mode 100: push-pull mode, pp_en=1 101: nmos open drain mode, odn_en=1 110: pmos open drain mode, odp_en=1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 analog io digital out digital out oe odn_en oe odn_en digital out oe 2x_en pp_en 2x_en odp_en digital out oe pp_en odp_en vdd2 vdd2 vdd2
000-0046121--106 page 30 of 97 SLG46121 8.0 connection matrix the connection matrix in the sl g46121 is used to create the int ernal routing for internal functions of the device once it is programmed. the registers are pr ogrammed from the one-time nvm cell during test mode operatio n. all of the connection points for each logic cell within the sl g46121 have a specific digital bit code assigned to it that is either set to active high or inactive low based on the design that is created. once the 768 registe r bits within the SLG46121 are pr ogrammed a fully custom circui t will be created. the connection matrix has 40 inpu ts and 64 outputs. each of the 40 inputs to the connection matrix is hard-wired to a particul ar source macrocell, including i/o pins, luts, analog comparators, other digital resources and v dd and v ss . the input to a digital macrocell uses a 6-bit register to select one of these 40 input lines. for a complete list of the slg 46121s register t able, see secti on 17.0 appendix a - slg461 21 register definition. figure 7. connection matrix figure 8. connection matrix example vss 0 pin 2 digital in 1 pin 3 digital in 2 pin 4 digital in 3 matrix input signal functions n pin12 digital in 38 vdd 39 n function registers 63 pin10 output en- able reg <383:378> 0 pin3 digital output source reg <5:0> 1 pin4digital output source reg <11:6> 2 pin5 digital output source reg <17:12> matrix inputs matrix outputs pin 2 pin 3 pin 10 connection matrix lut pin 3 pin 2 lut pin 10 function
000-0046121--106 page 31 of 97 SLG46121 8.1 matrix input table table 15. matrix input table n matrix input signal function matrix decode 5 4 3 2 1 0 0 vss 000000 1 pin2 digital input 0 0 0 0 0 1 2 pin3 digital input 0 0 0 0 1 0 3 pin4 digital input 0 0 0 0 1 1 4 pin5 digital input 0 0 0 1 0 0 5 pin6 digital input 0 0 0 1 0 1 6 lut2_0 output (dff/latch_0 output) 0 0 0 1 1 0 7 lut2_1 output (dff/latch_1 output) 0 0 0 1 1 1 8 lut2_2 output (dff/latch_2 output) 0 0 1 0 0 0 9 lut2_3 output (dff/latch_3 output) 0 0 1 0 0 1 10 lut2_4 output 0 0 1 0 1 0 11 sig_1pipe_dly_out (1st stage pipe delay output) 0 0 1 0 1 1 12 lut3_0 output (dff/latch_4 out put with resetb or seb) 0 0 1 1 0 0 13 lut3_1 output (dff/latch_5 out put with resetb or seb) 0 0 1 1 0 1 14 lut3_2 output (dff/latch_6 out put with resetb or seb) 0 0 1 1 1 0 15 lut3_3 output (dff/latch_7 out put with resetb or seb) 0 0 1 1 1 1 16 lut3_4 output 0 1 0 0 0 0 17 lut3_5 output 0 1 0 0 0 1 18 lut3_6 output 0 1 0 0 1 0 19 lut3_7 output 0 1 0 0 1 1 20 lut3_8 output (pipe delay output0) 0 1 0 1 0 0 21 lut4_0 output (cnt_dly3 output (8 bit w/ ext ck,reset)) 0 1 0 1 0 1 22 lut4_1 output (cnt_dly4 output (8 bit w/ ext ck,reset)) 0 1 0 1 1 0 23 cnt_dly0(14bit) output 0 1 0 1 1 1 24 cnt_dly1 output (8 bit w/ ext ck,reset) 0 1 1 0 0 0 25 edge detector output from cnt_dly4 0 1 1 0 0 1 26 acmp_0 output 0 1 1 0 1 0 27 acmp_1 output 0 1 1 0 1 1 28 pipe delay output1 0 1 1 1 0 0 29 programmable delay with edge detector output (deglitch filter o ut- put) 011101 30 internal oscillator output (one o f /1, /2, /3, /4 , /8, /12, /24 , /64 se- lected by reg) 011110 31 internal oscillator output (one o f /1, /2, /3, /4 , /8, /12, /24 , /64 se- lected by reg) 011111 32 bandgap ok signal 1 0 0 0 0 0 33 resetb_core as matrix input 1 0 0 0 0 1 34 pin8 digital input 1 0 0 0 1 0 35 pin9 digital input 1 0 0 0 1 1
000-0046121--106 page 32 of 97 SLG46121 36 pin10 digital input 1 0 0 1 0 0 37 inverter inv_0 output 1 0 0 1 0 1 38 pin12 digital input 1 0 0 1 1 0 39 vdd 100111 table 15. matrix input table n matrix input signal function matrix decode 5 4 3 2 1 0
000-0046121--106 page 33 of 97 SLG46121 8.2 matrix output table table 16. matrix output table register bit address matrix output signal function matrix output number reg <5:0> pin 3 digital out source 0 reg <11:6> pin 4 digital out source 1 reg <17:12> pin 5 digital out source 2 reg <23:18> pin 6 digital out source 3 reg <29:24> pin 6 output enable 4 reg <35:30> in0 of lut2 _0 (clock input of dff0) 5 reg <41:36> in1 of lut2_0 (data input of dff0) 6 reg <47:42> in0 of lut2 _1 (clock input of dff1) 7 reg <53:48> in1 of lut2_1 (data input of dff1) 8 reg <59:54> in0 of lut2 _2 (clock input of dff2) 9 reg <65:60> in1 of lut2_2 (data input of dff2) 10 reg <71:66> in0 of lut2_3 (clock input of dff3) 11 reg <77:72> in1 of lut2_3 (data input of dff3) 12 reg <83:78> in0 of lut2_4 13 reg <89:84> in1 of lut2_4 14 reg <95:90> in0 of inverter inv_0 15 reg <101:96> pin 12 digital out source 16 reg <107:102> in0 of l ut3_0 (clock input of dff4 with nreset/nse t) 17 reg <113:108> in1 of lut 3_0 (data input of d ff4 with nreset/nset )18 reg <119:114> in2 of l ut3_0 (resetb or setb of dff4 with nreset /nset) 19 reg <125:120> in0 of l ut3_1 (clock input of dff5 with nreset/nse t) 20 reg <131:126> in1 of lut 3_1 (data input of d ff5 with nreset/nset )21 reg <137:132> in2 of l ut3_1 (resetb or setb of dff5 with nreset /nset) 22 reg <143:138> in0 of l ut3_2 (clock input of dff6 with nreset/nse t) 23 reg <149:144> in1 of lut 3_2 (data input of d ff6 with nreset/nset )24 reg <155:150> in2 of l ut3_2 (resetb or setb of dff6 with nreset /nset) 25 reg <161:156> in0 of l ut3_3 (clock input of dff7 with nreset/nse t) 26 reg <167:162> in1 of lut 3_3 (data input of d ff7 with nreset/nset )27 reg <173:168> in2 of l ut3_3 (resetb or setb of dff7 with nreset /nset) 28 reg <179:174> in0 of lut3_4 29 reg <185:180> in1 of lut3_4 30 reg <191:186> in2 of lut3_4 31 reg <197:192> in0 of lut3_5 32 reg <203:198> in1 of lut3_5 33 reg <209:204> in2 of lut3_5 34 reg <215:210> in0 of lut3_6 35 reg <221:216> in1 of lut3_6 36 reg <227:222> in2 of lut3_6 37
000-0046121--106 page 34 of 97 SLG46121 reg <233:228> in0 of lut3_7 38 reg <239:234> in1 of lut3_7 39 reg <245:240> in2 of lut3_7 40 reg <251:246> in0 of lut3_8 (input of pipe delay) 41 reg <257:252> in1 of lut3_8 (resetb of pipe delay) 42 reg <263:258> in2 of lut3_ 8 (clock of pipe delay) 43 reg <269:264> in0 of lut4_0 (input for delay2 ext. clock or coun ter2 8bit external clock) 44 reg <275:270> in1 of lut 4_0 (input for delay 2 or counter2 reset input) 45 reg <281:276> in2 of lut4_0 46 reg <287:282> in3 of lut4_0 47 reg <293:288> in0 of lut4_1 (input for delay3 ext. clock or coun ter3 8bit external clock) 48 reg <299:294> in1 of lut 4_1 (input for delay 3 or counter3 reset input) 49 reg <305:300> in2 of lut4_1 50 reg <311:306> in3 of lut4_1 51 reg <317:312> input for delay0 o r counter0 (14bits) external clo ck 52 reg <323:318> input for delay1 ex t. clock or counter1 8bit exter nal clock 53 reg <329:324> input for dela y1 or counter1 reset input 54 reg <335:330> not used 55 reg <341:336> pdb for acmp0 56 reg <347:342> pdb for acmp1 57 reg <353:348> input for programm able delay for edg e detector (de glitch filter input) 58 reg <359:354> power down for osc. ( higher priority) (high = powe r down). 59 reg <365:360> pin 8 di gital out source 60 reg <371:366> pin 9 digital out source 61 reg <377:372> pin 10 digital out source 62 reg <383:378> pin 10 output enable 63 table 16. matrix output table register bit address matrix output signal function matrix output number
000-0046121--106 page 35 of 97 SLG46121 9.0 combinatorial logic combinatorial logic is supported via five lookup tables (luts) within the SLG46121. there is one 2-bit lut and four 3-bit luts . the device also includes 11 combination function macrocells tha t can be used as luts. for more details, please see section 10.0 combination function macrocells. inputs/outputs for the four lut s are configured from the connec tion matrix with specific logic functions being defined by the state of nvm bits. the outputs of the luts can be configured to any u ser defined function, including the following standard digital logic devices (and, nand, or, nor, xor, xnor). 9.1 2-bit lut the one 2-bit lut takes in two input signals from the connectio n matrix and produce a single out put, which goes back into the connection matrix. .. each 2-bit lut uses a 4-bit regi ster signal to define their out put functions; 2-bit lut4 is defined by reg <415:412> the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the t wo 2-bit lut logic cells. figure 9. 2-bit lut table 18. 2-bit lut stand ard digital functions. function msb lsb and-2 1000 nand-2 0 1 1 1 or-2 1110 nor-2 0 0 0 1 xor-2 0110 xnor-2 1001 2-bit lut4 out in1 in0 reg <415:412> from connection matrix output <13> from connection matrix output <14> to connection matrix input <10> table 17. 2-bit lut4 truth table. in1 in0 out 0 0 reg <412>reg 0 1 reg <413>reg 1 0 reg <414>reg 1 1 reg <415>reg
000-0046121--106 page 36 of 97 SLG46121 9.2 3-bit lut the four 3-bit luts each take in three input signals from the c onnection matrix and produce a single output, which goes back i nto the connection matrix. figure 10. 3-bit luts 3-bit lut4 out in1 in0 reg <463:456> from connection matrix output <29> from connection matrix output <30> to connection matrix input <16> 3-bit lut5 out in1 in0 reg <471:464> from connection matrix output <32> from connection matrix output <33> to connection matrix input <17> in2 from connection matrix output <31> in2 from connection matrix output <34> 3-bit lut6 out in1 in0 reg <479:472> from connection matrix output <35> from connection matrix output <36> to connection matrix input <18> 3-bit lut7 out in1 in0 reg <487:480> from connection matrix output <38> from connection matrix output <39> to connection matrix input <19> in2 from connection matrix output <37> in2 from connection matrix output <40> table 19. 3-bit lut4 truth table. in2 in1 in0 out 0 0 0 reg <456> 0 0 1 reg <457> 0 1 0 reg <458> 0 1 1 reg <459> 1 0 0 reg <460> 1 0 1 reg <461> 1 1 0 reg <462> 1 1 1 reg <463> table 20. 3-bit lut5 truth table. in2 in1 in0 out 0 0 0 reg <464> 0 0 1 reg <465> 0 1 0 reg <466> 0 1 1 reg <467> 1 0 0 reg <468> 1 0 1 reg <469> 1 1 0 reg <470> 1 1 1 reg <471> table 21. 3-bit lut6 truth table. in2 in1 in0 out 0 0 0 reg <472> 0 0 1 reg <473> 0 1 0 reg <474> 0 1 1 reg <475> 1 0 0 reg <476> 1 0 1 reg <477> 1 1 0 reg <478> 1 1 1 reg <479> table 22. 3-bit lut7 truth table. in2 in1 in0 out 0 0 0 reg <480> 0 0 1 reg <481> 0 1 0 reg <482> 0 1 1 reg <483> 1 0 0 reg <484> 1 0 1 reg <485> 1 1 0 reg <486> 1 1 1 reg <487>
000-0046121--106 page 37 of 97 SLG46121 each 3-bit lut uses a 8-bit regi ster signal to define their out put functions; 3-bit lut4 is defined by reg <463:456> 3-bit lut5 is defined by reg <471:464> 3-bit lut6 is defined by reg <479:472> 3-bit lut7 is defined by reg <487:480> the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the two 3-bit lut logic cells. table 23. 3-bit lut stand ard digital functions. function msb lsb and-3 10000000 nand-3 01111111 or-3 11111110 nor-3 00000001 xor-3 10010110 xnor-3 01101001
000-0046121--106 page 38 of 97 SLG46121 10.0 combination function macrocells the SLG46121 has twelve combination function macrocells that ca n serve more than one logic or timing function. in elven of these cases, they can serve as a look up table (lut), or as ano ther logic or timing function. in the last case, it can serve a s either a programmable delay or deglitch filter. see the list be low for the functions that can be implemented in these macrocel ls. ? four macrocells that can serve as either 2-bit luts or as d fl ip flops ? four macrocells that can serve as either 3-bit luts or as d fl ip flops ? one macrocell that can serve as either 3-bit lut or as pipe de lay ? two macrocells that can serve as either 4-bit luts or as 8-bit counter / delays ? one macrocell that can serve as either a progra mmable delay or as a deglitch filter inputs/outputs for the eleven combination function macrocells a re configured from the connection matrix with specific logic functions being defined by the state of nvm bits. when used as a lut to implement combinatorial logic functions, the outputs of the luts can be configured to any user defined function, including th e following standard digital logic device s (and, nand, or, nor, xor, xnor). when used as a d flip flop / latch, the source and destination of the inputs and outputs for th e dff/latches are configured fr om the connection matrix. all dff/la tch macrocells have user selec tion for initial state, and all h ave the option to connect both the q and q bar outputs to the connection matrix. the macrocells df f4, dff5, dff6 and dff7 have an additional input from the matrix that can serve as a nset o r nreset function to the macro cell. the operation of the d flip-flop and latch will follow the func tional descriptions below: dff: clk is rising edge triggered , then q = d; otherwise q will not change latch: if clk = 0, then q = d 10.1 2-bit lut or d flip flop macrocells there are four macrocells that c an serve as either 2-bit luts o r as d flip flops. when used to implement lut functions, the 2- bit luts each take in two input signals from the connection matrix and produce a single output, which goes back into the connectio n matrix. when used to implement d flip flop function, the two in put signals from the connection matrix go to the data (d) and c lock (clk) inputs for the flip flop, with the outpu t going back to t he connection matrix.
000-0046121--106 page 39 of 97 SLG46121 figure 11. 2-bit lut0 or dff0 figure 12. 2-bit lut1 or dff1 dff0 2-bit lut0 to connection matrix input <6> from connection matrix output <6> reg <399:396> reg <420> from connection matrix output <5> clk d out in0 in1 4-bits nvm 1-bit nvm q/nq reg <397> output select (q or nq) dff1 2-bit lut1 from connection matrix output <8> reg <403:400> from connection matrix output <7> to connection matrix input <7> reg <421> clk d out in0 in1 4-bits nvm 1-bit nvm q/nq reg <401> output select (q or nq)
000-0046121--106 page 40 of 97 SLG46121 figure 13. 2-bit lut2 or dff2 figure 14. 2-bit lut3 or dff3 dff2 2-bit lut2 to connection matrix input <8> from connection matrix output <10> reg <407:404> from connection matrix output <9> reg <422> clk d out in0 in1 4-bits nvm 1-bit nvm q/nq reg <405> output select (q or nq) dff3 2-bit lut3 from connection matrix output <12> reg <411:408> from connection matrix output <11> to connection matrix input <9> reg <423> clk d out in0 in1 4-bits nvm 1-bit nvm q/nq reg <409> output select (q or nq) 2-bit lut3
000-0046121--106 page 41 of 97 SLG46121 10.1.1 2-bit lut or d flip flop macrocells used as 2-bit luts each macrocell, when programmed for a lut function, uses a 4-bi t register to define their output function: 2-bit lut0 is defined by reg <399:396> 2-bit lut1 is defined by reg <403:400> 2-bit lut2 is defined by reg <407:404> 2-bit lut3 is defined by reg <411:408> table 24. 2-bit lut0 truth table. in1 in0 out 0 0 reg <396> 0 1 reg <397> 1 0 reg <398> 1 1 reg <399> table 25. 2-bit lut1 truth table. in1 in0 out 0 0 reg <400> 0 1 reg <401> 1 0 reg <402> 1 1 reg <403> table 26. 2-bit lut3 truth table. in1 in0 out 0 0 reg <404> 0 1 reg <405> 1 0 reg <406> 1 1 reg <407> table 27. 2-bit lut4 truth table. in1 in0 out 0 0 reg <408> 0 1 reg <409> 1 0 reg <410> 11 reg <411>
000-0046121--106 page 42 of 97 SLG46121 10.1.2 2-bit lut or d flip flop macrocells used as d flip flo p register settings table 28. dff0 register settings signal function register bit address register definition dff0 or latch select reg <396> 0: dff function 1: latch function dff0 output select reg <397> 0: q output 1: nq output dff0 initial polarity select reg <398> 0: low 1: high lut2_0 data reg < 399:396> lut2_0 data lut2_0 or dff0 select reg <420> 0: lut2_0 1: dff0 table 29. dff1 register settings signal function register bit address register definition dff1 or latch select reg <400> 0: dff function 1: latch function dff1 output select reg <401> 0: q output 1: nq output dff1 initial polarity select reg <402> 0: low 1: high lut2_1 data reg < 403:400> lut2_1 data lut2_1 or dff1 select reg <421> 0: lut2_1 1: dff1 table 30. dff2 register settings signal function register bit address register definition dff2 or latch select reg <404> 0: dff function 1: latch function dff2 output select reg <405> 0: q output 1: nq output dff2 initial polarity select reg <406> 0: low 1: high lut2_2 data reg < 407:404> lut2_2 data lut2_2 or dff2 select reg <422> 0: lut2_2 1: dff2
000-0046121--106 page 43 of 97 SLG46121 table 31. dff3 register settings signal function register bit address register definition dff3 or latch select reg <408> 0: dff function 1: latch function dff3 output select reg <409> 0: q output 1: nq output dff3 initial polarity select reg <410> 0: low 1: high lut2_3 data reg <411:408> lut2_3 data lut2_3 or dff3 select reg <423> 0: lut2_3 1: dff3
000-0046121--106 page 44 of 97 SLG46121 10.2 3-bit lut or d flip flop with set/reset macrocells there are four macrocells that c an serve as either 3-bit luts o r as d flip flops. when used to implement lut functions, the 3- bit luts each take in three input signals from the connection matri x and produce a single output, which goes back into the connect ion matrix. when used to implement d flip flop function, the three input signals from the connection matrix go to the data (d) and clock (clk) and set/re set (nrst/nset) inputs for the flip flop, with the output going back to the connection matrix.. figure 15. 3-bit lut0 or dff4 figure 16. 3-bit lut1 or dff5 dff4 to connection matrix< input 12> from connection matrix output <19> 3-bit lut0 from connection matrix output <18> from connection matrix output <17> reg <431:424> clk d 8-bits nvm 1-bit nvm out in1 in2 in0 nrst/nset reg <496> reg <425> output select (q or nq) q/nq 3-bit lut0 dff5 3-bit lut1 from connection matrix output <22> from connection matrix output <21> from connection matrix output <20> reg <439:432> to connection matrix< input 13> clk d 8-bits nvm 1-bit nvm out in1 in2 in0 nrst/nset reg <497> reg <433> output select (q or nq) q/nq
000-0046121--106 page 45 of 97 SLG46121 figure 17. 3-bit lut2 or dff6 figure 18. 3-bit lut3 or dff7 dff6 to connection matrix< input 14> from connection matrix output <25> 3-bit lut2 from connection matrix output <24> from connection matrix output <23> reg <447:440> clk d 8-bits nvm 1-bit nvm out in1 in2 in0 nrst/nset reg <498> reg <441> output select (q or nq) q/nq dff7 3-bit lut3 from connection matrix output <28> from connection matrix output <27> from connection matrix output <26> reg <455:448> to connection matrix< input 15> clk d 8-bits nvm 1-bit nvm out in1 in2 in0 nrst/nset reg <499> reg <449> output select (q or nq) q/nq
000-0046121--106 page 46 of 97 SLG46121 10.2.1 3-bit lut or d flip flop macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut0 is defined by reg <431:424> 3-bit lut1 is defined by reg <439:432> 3-bit lut2 is defined by reg <447:440> 3-bit lut3 is defined by reg <455:448> table 32. 3-bit lut0 truth table. in2 in1 in0 out 0 0 0 reg <424> 0 0 1 reg <425> 0 1 0 reg <426> 0 1 1 reg <427> 1 0 0 reg <428> 1 0 1 reg <429> 1 1 0 reg <430> 1 1 1 reg <431> table 33. 3-bit lut1 truth table. in2 in1 in0 out 0 0 0 reg <432> 0 0 1 reg <433> 0 1 0 reg <434> 0 1 1 reg <435> 1 0 0 reg <436> 1 0 1 reg <437> 1 1 0 reg <438> 1 1 1 reg <439> table 34. 3-bit lut2 truth table. in2 in1 in0 out 0 0 0 reg <440> 0 0 1 reg <441> 0 1 0 reg <442> 0 1 1 reg <443> 1 0 0 reg <444> 1 0 1 reg <445> 1 1 0 reg <446> 1 1 1 reg <447> table 35. 3-bit lut3 truth table. in2 in1 in0 out 0 0 0 reg <448> 0 0 1 reg <449> 0 1 0 reg <450> 0 1 1 reg <451> 1 0 0 reg <452> 1 0 1 reg <453> 1 1 0 reg <454> 1 1 1 reg <455>
000-0046121--106 page 47 of 97 SLG46121 10.2.2 3-bit lut or d flip flop macrocells used as d flip flo p register settings table 36. dff4 register settings signal function register bit address register definition dff4 or latch select reg <424> 0: dff function 1: latch function dff4 output select reg <425> 0: q output 1: nq output dff4 rstb/setb select reg <426> 1: setb from matrix out 0: resetb from matrix out dff4 initial polarity select reg <427> 0: low 1: high lut3_0 data reg < 431:424> lut3_0 data lut3_0 or dff4 select reg <496> 0: lut3_0 1: dff4 table 37. dff5 register settings signal function register bit address register definition dff5 or latch select reg <432> 0: dff function 1: latch function dff5 output select reg <433> 0: q output 1: nq output dff5 rstb/setb select reg <434> 1: setb from matrix out 0: resetb from matrix out dff5 initial polarity select reg <435> 0: low 1: high lut3_1 data reg < 439:432> lut3_1 data lut3_1 or dff5 select reg <497> 0: lut3_1 1: dff5 table 38. dff6 register settings signal function register bit address register definition dff6 or latch select reg <440> 0: dff function 1: latch function dff6 output select reg <441> 0: q output 1: nq output dff6 rstb/setb select reg <442> 1: setb from matrix out 0: resetb from matrix out dff6 initial polarity select reg <443> 0: low 1: high lut3_2 data reg < 447:440> lut3_2 data lut3_2 or dff6 select reg <498> 0: lut3_2 1: dff6
000-0046121--106 page 48 of 97 SLG46121 table 39. dff7 register settings signal function register bit address register definition dff7 or latch select reg <448> 0: dff function 1: latch function dff7 output select reg <449> 0: q output 1: nq output dff7 rstb/setb select reg <450> 1: setb from matrix out 0: resetb from matrix out dff7 initial polarity select reg <451> 0: low 1: high lut3_3 data reg < 455:448> lut3_3 data lut3_3 or dff7 select reg <499> 0: lut3_3 1: dff7
000-0046121--106 page 49 of 97 SLG46121 10.3 3-bit lut or pipe delay macrocell there is one macrocell that can serve as either a 3-bit lut or as a pipe delay. when used to implement lut functions, the 3-bit lut take in thr ee input signals from the connection matrix and produces a sing le output, which goes back in to the connection matrix. when used as an 8-stage pipe delay, there are three inputs sign als from the matrix, input (in), clock (clk) and reset (nreset) . the pipe delay macrocell is built from 8 d flip-flop logic cell s that provide three register shi fted options, two of which are user selectable. the dff cells are tied in series where the output ( q) of each delay cell goes to the next dff cell. the first dela y option (1 pipe out) is fixed at the output of the first flip-flop stag e. the other two outputs (out0 and out1) provide user selectabl e options for 1 to 8 stages of delay. the overall time of the delay is based on the clock used in the SLG46121 design. each dff cell has a time delay of the inverse of the clock time (either extern al clock or the r c oscillator w ithin the SLG46121). th e sum of the number of dff cells used wi ll be the total time delay of th e pipe delay logic cell. figure 19. 3-bit lut4 or pipe delay 3-bit lut8 out in1 in0 reg <495:488> from connection matrix output <41> from connection matrix output <42> in2 from connection matrix output <43> 8 flip-flops in nreset ck from connection matrix output <42> from connection matrix output <41> from connection matrix output <43> reg <493:491> reg <490:488> to connection matrix input<28> out1 out0 reg <690> 1 0 to connection matrix input<20> reg <500> 0 1 to connection matrix input<11> pipe out
000-0046121--106 page 50 of 97 SLG46121 10.3.1 3-bit lut or pipe delay macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut8 is defined by reg <495:488> 10.3.2 3-bit lut or pipe del ay macrocells used as pipe delay register settings table 41. pipe delay register settings signal function register bit address register definition out0 select reg <490:488> data (pipe number) out1 select reg <493:491> data (pipe number) unused if pipe delay selected reg <495:494> unused lut3_8 or pipe de- lay output select reg <500> 0: lut3_8 1: pipe delay table 40. 3-bit lut8 truth table. in2 in1 in0 out 0 0 0 reg <488> 0 0 1 reg <489> 0 1 0 reg <490> 0 1 1 reg <491> 1 0 0 reg <492> 1 0 1 reg <493> 1 1 0 reg <494> 1 1 1 reg <495>
000-0046121--106 page 51 of 97 SLG46121 10.4 4-bit lut or 8- bit counter / delay macrocells there are two macrocells that can serve as either a 4-bit lut o r as a counter / delay. when used to implement lut functions, the 4-bit lut takes in four input signals from the connection m atrix and produces a single ou tput, which goes back into the connection matrix. when used to implement 8-bit counter / delay function, two of the four input signals from the connection ma trix go to the external clock (ext_clk) and reset (dly_n/cnt_reset) for the counter/delay, with the output going back to the connec tion matrix. figure 20. 4-bit lut0 or cnt/dly2 cnt/dly2 out clk dly_n/cnt_reset 4-bit lut0 out in0 in1 16-bits nvm 1-bit nvm in2 in3 to connection matrix input <21> from connection matrix output <45> reg <516:501> reg <517> from matrix output <44> from connection matrix output <47> from connection matrix output <46>
000-0046121--106 page 52 of 97 SLG46121 figure 21. 4-bit lut1 or cnt/dly3 cnt/dly3 out clk dly_n/cnt_reset 4-bit lut1 out in0 in1 16-bits nvm 1-bit nvm in2 in3 to connection matrix input <22> from connection matrix output <49> reg <533:518> reg <534> from connection matrix output <48> from connection matrix output <51> from connection matrix output <50>
000-0046121--106 page 53 of 97 SLG46121 10.4.1 4-bit lut or 8-bit counter / delay macrocell used as 4 -bit luts each macrocell, when programmed for a lut function, uses a 16-b it register to define their output function: 4-bit lut0 is defined by reg <516:501> 4-bit lut1 is defined by reg <533:518> table 44. 4-bit lut standard digital functions. function msb lsb and-4 1000000000000000 nand-40111111111111111 or-4 1111111111111110 nor-4 0000000000000001 xor-4 0110100110010110 xnor-41001011001101001 table 42. 4-bit lut0 truth table. in3 in2 in1 in0 out 0000reg < 501> 0001reg < 502> 0010reg < 503> 0011reg < 504> 0100reg < 505> 0101reg < 506> 0110reg < 507> 0111reg < 508> 1000reg < 509> 1001reg < 510> 1010reg <511> 1011reg < 512> 1100reg < 513> 1101reg < 514> 1110reg < 515> 1111reg < 516> table 43. 4-bit lut1 truth table. in3 in2 in1 in0 out 0 0 0 0 reg <518> 0 0 0 1 reg <519> 0 0 1 0 reg <520> 0 0 1 1 reg <521> 0 1 0 0 reg <522> 0 1 0 1 reg <523> 0 1 1 0 reg <524> 0 1 1 1 reg <525> 1 0 0 0 reg <526> 1 0 0 1 reg <527> 1 0 1 0 reg <528> 1 0 1 1 reg <529> 1 1 0 0 reg <530> 1 1 0 1 reg <531> 1 1 1 0 reg <532> 1 1 1 1 reg <533>
000-0046121--106 page 54 of 97 SLG46121 10.4.2 4-bit lut or 8-bit counter / delay macrocells used as 8-bit counter / delay register settings table 45. cnt/dly2 register settings signal function register bit address register definition counter/delay2 mode selection reg <501> 0: delay mode 1: counter mode counter/delay2 clock source select reg <504:502> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter1 overflow counter/delay2 control data reg <512:505> 1 C 256 (delay time = (counter contro l data +2) /f req) delay2 mode select or asynchronous counter reset reg <514:513> 00: delay on both f alling and risi ng edges (for de lay & counter reset) 01: delay on falling edge only (f or delay & counter reset delay ) 10: on rising edge only (f or delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode lut4_0 or count- er2 select reg <517> 0: lut4_0 1: counter2 table 46. cnt/dly3 register settings signal function register bit address register definition counter/delay3 mode selection reg <518> 0: delay mode 1: counter mode counter/delay3 clock source select reg <521:519> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter2 overflow counter/delay3 control data reg <529:522> 1 C 256 (delay time = (counter contro l data +2) /f req) delay3 mode select or asynchronous counter reset reg <531:530> 00: delay on both f alling and risi ng edges (for de lay & counter reset) 01: delay on falling edge only (f or delay & counter reset delay ) 10: on rising edge only (f or delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode lut4_1 or count- er3 select reg <534> 0: lut4_1 1: counter3
000-0046121--106 page 55 of 97 SLG46121 10.5 programmable delay / edge detector the SLG46121 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four timings (time1) configured in the greenpak designer. the progra mmable time delay cell can generate one of four different delay patterns, rising edge detection , falling edge detection, both e dge detection and both edge delay. these four patterns can be f urther modified with the addition of delayed edge detection, which add s an extra unit of delay as well as glitch rejection during the delay period. see the timing diagrams b elow for further information. note : the input signal must be longer than the delay, otherwise it will be filtered out. 10.6 programmable delay timing diagram - edge detector output figure 22. programmable delay figure 23. edge detector output programmable delay out in reg <743:742> from connection matrix output <58> to connection matrix input <29> reg <745:744> edge mode selection delay value selection 1 0 reg <746> deglitch filter out 1 0 reg <746> deglitch filter in time1 edge detector output in rising edge detector falling edge detector both edge detector both edge delay time1 time1 can be set by register
000-0046121--106 page 56 of 97 SLG46121 note: for delays and widths refer to table 4 . figure 24. delayed edge detector output delayed edge detector output delayed rising edge detector delayed falling edge detector delayed both edge detector delayed both edge delay time2 time2 time1 can be set by register time2 is a fixed value in time1 time1
000-0046121--106 page 57 of 97 SLG46121 10.6.1 programmable de lay register settings table 47. programmable de lay register settings signal function register bit address register definition programmable delay or filter output select reg <746> 0: programmable delay output 1: filter output select the edge mode of programmable delay & edge detector reg <745:744> 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay delay value select for programmable delay & edge detector (vdd = 3.3v, typical condition) reg <743:742> 00: 163 ns 01: 305 ns 10: 446 ns 11: 588 ns
000-0046121--106 page 58 of 97 SLG46121 10.7 deglitch filter the SLG46121 has an additional logic function that is connected directly to the connection matrix inputs and outputs. there is one deglitch filter. figure 25. deglitch filter deglich filter in deglitch filter out filter reg <699> c r
000-0046121--106 page 59 of 97 SLG46121 11.0 analog comparators (acmp) there are two analog comparator ( acmp) macrocells in the slg461 20. in order for the acmp cel ls to be used in a greenpak design, the power up signals (acmp0_pdb and acmp1_pdb) need to be active. by connecting to signals coming from the connection matrix, it is possible to have each acmp be on conti nuously, off continuously, or switched on periodically based on a digital signal coming from the connection matrix. when acmp i s powered down, output is low. each of the acmp cells has a positive input signal that can be provided by a variety of exter nal sources, and can also have a selectable gain stage before connection to the analog comparato r. each of the acmp cells has a negative input signal that is either created from an internal v ref or provided by way of the external sources. each of the acmp cells has a selection for the bandwidth of the input signal, which can be used to save power when low bandwid th signals are input into the analog comparator. and if input freq uency > 200 khz, the output will retain its previous value. eac h cell also has a hysteresis selection , to offer hysteresis of 0 mv, 2 5 mv, 50 mv or 200 mv. during powerup, the acmp output will remain low, and then becom e valid 110 s (max) after por signal goes high, see figure 26 . note: applies to first time power on. note: regulator and charge pump set to automatic on/off. each of the acmp cells has a positive input signal that can be provided by a variety of exter nal sources, and can also have a selectable gain stage (1x, 0.5x, 0.33x, 0.25x) before connectio n to the analog comparator. the gain divider is unbuffered and consists of 250 k? (typ.) resistors, see table 48 . for gain divider accuracy refer to table 49 . in- voltage range: 0 - 1.2 v. can use vref selection v dd/4 and vdd/3 to maint ain this input range . figure 26. maximum power on delay vs. vdd. table 48. gain di vider input resistance (typ). gain 1x 0.5x 0.33x 0.25x input resistance 100m 1m 0.75m 1m table 49. gain di vider accuracy. gain 0.5x 0.33x 0.25x accuracy 0.6% 0.9% 0.28% 1 2 3 4 5 6 7 8 9 10 11 12 power on delay (s) 0 0 0 0 0 0 0 0 0 0 0 0 0 1.71 1.80 1.89 2.50 2.70 3.00 330 vdd (v) 3 . 30 3.60 4.20 4.50 -3 5 ro o +8 5 5.00 5.50 5 ? c o m 5 ? c
000-0046121--106 page 60 of 97 SLG46121 each of the acmp cells has a negative input signal that is eith er created from an internal vref or provided by the external reference/source. in ternal vref accuracy is optimized near 1000 mv selection. note: power supply control options ha ve influence on the acmp operation. note: any acmp powered on enables the bandgap internal circui t as well. an analog voltage will appear on vref (even when the force bandgap option is set as disabled). analog comparators have the f ollowing configurable options: ? hysteresis: input signal hyster esis options are disable, 25 mv , 50 mv, 200 mv. ? low bandwidth: enable, disable; ? in+ gain: 1x, 0.5x, 0.33x, 0.25x; ? in+ source: ? acmp0 in+ options are pin 3, vdd; ? acmp1 in+ options are pin 6, acmp0 in+; ?in- source: ? acmp0 in- options are 24 internal reference sourc es (50 mv C 1 200 mv) and vdd/3, vdd/4, pin 4; ? pwr up=0 C acmp is powered down; pwr up=1 C acmp is powered up . all acmps can have a common negat ive input. this can be achieve d by configuring acmp0 pi n 4 analog i/o connection. 11.1 acmp0 block diagram figure 27. acmp0 block diagram 11010 11001- 00000 internal vref pin4: acmp0(-) 10 01 pin3: acmp0(+) external vdd 1.71 v ~ 5.5 v selectable gain reg <604:603> to acmp1 mux input vref + - from connection matrix output <56> pdb lbw selection ibias reg <605> hysteresis selection reg <602:601> l/s on after 100 ? s delay to connection matrix input<26> reg <600:596> *pin3_aio_en; reg <606> off after 1 ? s delay *pin3_aio_en: if reg <629:627> = 011 then 1, otherwise: 0
000-0046121--106 page 61 of 97 SLG46121 11.2 acmp0 register settings table 50. acmp0 register settings signal function register bit address register definition acmp0 in voltage select reg <600:596> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 0 1101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref (pin4) acmp0 hysteresis enable reg <602:601> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) acmp0 positive input divider reg <604:603> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp0 low bandwidth (max: 1 mhz) enable reg <605> 0: off 1: on acmp0 positive input source select pin3 and vdd reg <606> 0: pin3 1: vdd
000-0046121--106 page 62 of 97 SLG46121 11.3 acmp1 block diagram figure 28. acmp1 block diagram 11010 11001- 00000 internal vref pin4: acmp0(-) 10 01 pin6: acmp1(+) from acmp0s mux selectable gain reg <615:614> vref + - from connection matrix output <57> pdb lbw selection ibias reg <617> hysteresis selection reg <613:612> l/s on after 100 ? s delay to connection matrix input<27> reg <611:607> *pin6_aio_en; reg <618> off after 1 ? s delay *pin6_aio_en: if reg <29:24> = 00000 and reg <649:648> = 11 then 1, other wise: 0
000-0046121--106 page 63 of 97 SLG46121 11.4 acmp1 register settings table 51. acmp1 register settings signal function register bit address register definition acmp1 in voltage select reg <611:607> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 0 1101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref (pin4) acmp1 hysteresis enable reg <613:612> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) acmp1 positive input divider reg <615:614> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp1 100 ? a current source option reg <616> 0: disable 1hebrew : enable acmp1 low bandwidth (max: 1 mhz) enable reg <617> 1: on 0: off acmp1 positive input source select pin3 and pin6 reg <618> 0: pin6 1: pin3
000-0046121--106 page 64 of 97 SLG46121 11.5 typical performance characteristics note: when vdd < 1.8v voltage reference should not exceed 1100 mv. figure 29. typical input voltage offset vs. voltage reference a t room temperature, lbw mode C disable, vhys=0 mv, vdd=(1.7 C 5.5) v. figure 30. typical input threshold variation (including vref var iation, acmp offset) vs. voltage reference at room temper ature, lbw mode C disable, vhys =0 mv. -5 -4 -3 -2 -1 0 1 2 3 4 5 50 150 250 350 450 550 650 750 850 950 1050 1150 voffset (mv) voltage reference (mv) upper limit lower limit -6% -4% -2% 0% 2% 4% 6% 8% 50 150 250 350 450 550 650 750 850 950 1050 1150 input threshold variation (%) voltage reference (mv) upper limit @ vdd=(1.8-5.5)v lower limit @ vdd=(1.8-5.5)v upper limit @ vdd=1.7v lower limit @ vdd=1.7v
000-0046121--106 page 65 of 97 SLG46121 figure 31. input threshold ratio vs . voltage reference at vdd = (1.71 - 5.5) v, vh ys = 0, gain = 1 figure 32. input threshold voltage vih, vil vs. vdd at vref = 10 00 mv, gain = 1 -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 50 100 200 300 400 500 600 700 800 900 1000 1100 1200 input threshold (%) voltage reference (mv) low-to-high @ +85c high-to-low @ +85c low-to-high @ -20c high-to-low @ -20c -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 1.71 2.5 3 5.5 input threshold voltage vih, vil (mv) vdd (v) vih @ +85oc vih @ -35oc vil @ +85oc vil @ -35oc
000-0046121--106 page 66 of 97 SLG46121 figure 33. input threshold voltage vih, vil vs. hysteresis at vd d = 5.5 v, vref = 1000 mv. gain = 1 figure 34. input threshold voltage vih, vil vs. gai n at hysteres is = 0, vdd = 5.5 v, vref = 1000 mv table 52. built-in hy steresis tolerance. vhys (mv) vdd=(1.7-1.8) v vdd=(1.89-5.5) v vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv min max min max min max min max min max min max 25 18.9 26.4 17.3 26.1 13.0 24.6 18.8 26.5 17.8 26.1 15.6 25.5 50 40.3 50.4 37.9 50.1 28.9 47.7 40.3 50.5 39.5 50.1 34.5 49.5 200 180.5 208.4 172.9 210.7 153.5 217.2 180.6 207.7 180.2 210.8 166.5 211.9 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 0 25 50 200 input threshold voltage vih, vil (mv) hysteresis (mv) vih @ +85oc vih @ -35oc vil @ +85oc vil @ -35oc -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 1 0.5 0.33 0.25 input threshold voltage vih, vil (mv) gain vih @ +85oc vih @ -35oc vil @ +85oc vil @ -35oc
000-0046121--106 page 67 of 97 SLG46121 11.6 timing characteristics figure 35. maximum propag ation delay low-to-high vs. voltage reference at room temperature, vod = 2 mv. figure 36. maximum propag ation delay low-to-high vs. voltage reference at room temperature, vdd=(1.71 C 1.89) v. 0 5 10 15 20 25 30 35 40 45 50 55 60 50 propagation delay low-to-hogh (s) 150 250 350 450 vol t vdd= vdd= 3 vdd= 5 450 550 650 750 t age referenc e 1.7 v 3 .3 v 5 .5 v 850 950 1050 1150 e (mv) 1150 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200 figure 37. maximum propag ation delay high-to-low vs. voltage reference at room temperature, vod = 2 mv. figure 38. maximum propag ation delay high-to-low vs. voltage reference at room temperature, vdd=(1.71 C 1.89) v. 0 5 10 15 20 25 30 35 40 45 50 55 60 50 propagation delay high-to-low (s) 150 250 350 450 volt a vdd= 3 vdd= 5 vdd= 1 550 650 750 ge reference ( 3 .3 v 5 .5 v 1 .7 v 850 950 1050 1150 ( mv) 1150 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200
000-0046121--106 page 68 of 97 SLG46121 figure 39. maximum propag ation delay low-to-high vs. voltage reference at room temperature, vdd = (1.89 C 3.6) v. figure 40. maximum propag ation delay low-to-high vs. voltage reference at room temperature, vdd = (3.6 C 5.5) v. 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200 figure 41. maximum propag ation delay high-to-low vs. voltage reference at room temperature, vdd = (1.89 C 3.6) v. figure 42. maximum propag ation delay high-to-low vs. voltage reference at room temperature, vdd = (3.6 C 5.5) v. 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200 0.25 0.5 1 2 4 8 16 32 64 128 256 512 1024 100 propagation delay low-to-hogh (s) 200 300 400 500 vol t vod=2 vod=5 vod=1 0 vod=1 0 500 600 700 800 t age referenc e mv mv 0 mv 0 0 mv 800 900 1000 1100 e (mv) 1200
000-0046121--106 page 69 of 97 SLG46121 12.0 counters/delay generators (cnt/dly) there are two configurable counters/delay generators in the slg 46121. cnt/dly0 is 14-bit and cnt/dly2 is 8-bit. for flexibilit y, each of these macrocells has a large selection of internal and external clock sources, as well a s the option to chain from the output of the previous (n-1) cnt/dly macrocell, to implement longer co unt / delay circuits. one of the counter/del ay generator macrocells (cnt/dly1) has tw o inputs from the connection matrix, one for delay input/reset input (delay_in/reset_in), and one for an exter nal counter/cloc k source. note that there are also two combination function macrocells th at can implemented as either 4-bit luts or 8-bit counter / dela ys, for more information please see se ction 10.4 4-bit lut or 8- bi t counter / delay macrocells. figure 43. cnt/dly0 cnt/dly0 counter_end clk to connection matrix input <23> from connection matrix output <52> count_end_out_x-1 reg <548> 0 1 2 3 4 5 6 7 ext. clock from cm out<52> rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <565:552> reg <551:549> 0 1 0 1 delay_out delay_in cnt clock edge detector
000-0046121--106 page 70 of 97 SLG46121 12.1 cnt/dly0 register settings figure 44. cnt/dly1 table 53. cnt/dly0 register settings signal function register bit address register definition counter/delay0 mode select reg <548> 0: delay mode 1: counter mode counter/delay0 clock source select (external clock is only for counter mode) reg <551:549> 000: i nternal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: reserved counter0 control data/delay0 time control reg <565:552> 1-16383: (delay time = (counter contr ol data +2) / freq) delay0 mode select or asynchronous counter reset reg <567:566> 00: delay on bo th falling and rising edges 01: delay on falling edge only 10: delay on rising edge only 11: no delay on either falling or rising edges cnt/dly1 counter_end clk to connection matrix input <24> from connection matrix output <54> count_end_out_x-1 reg <568> 0 1 2 3 4 5 6 7 ext. clock from cm out<53> rc osc/64 rc osc/24 rc osc/12 rc osc/4 rc osc counter control data reg <579:572> reg <571:569> 0 1 0 1 delay_out delay_in reset_in edge detector
000-0046121--106 page 71 of 97 SLG46121 12.2 cnt/dly1 register settings table 54. cnt/dly1 register settings signal function register bit address register definition counter/delay1 mode select reg <568> 0: delay mode 1: counter mode counter/delay1 clock source select (external clock is only for counter mode) reg <571:569> 000: i nternal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: reserved 111: counter0 overflow counter1 control data/delay1 time control reg <579:572> 1-256: (delay time = (counter control data +2) /fr eq) delay1 mode select or asynchronous counter reset reg <581:580> 00: delay on both f alling and risi ng edges (for de lay & counter reset) 01: delay on falling edge only (for delay & counter reset) 10: delay on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level res et for counter mode
000-0046121--106 page 72 of 97 SLG46121 13.0 voltage reference (vref) 13.1 voltage reference overview the SLG46121 has a voltage reference macrocell to provide refer ences to the four analog comparators. this macrocell can supply a user selectio n of fixed voltage references, /3 and /4 reference off of the v dd power supply to the dev ice, and externally supplied voltage references from pin 4. the macrocell also has the option to output reference voltages on pins 10. see table below for the available selections for each analog comparator. also see figure 45 below, which shows the reference output structure. 13.2 vref selection table table 55. vref selection table. sel<4:0> cmp0_vref cmp1_vref 11010 ext. vref (pin4) ext. vref (pin4) 11001 vdd / 4 vdd / 4 11000 vdd / 3 vdd / 3 10111 1.20 v 1.20 v 10110 1.15 v 1.15 v 10101 1.10 v 1.10 v 10100 1.05 v 1.05 v 10011 1.00 v 1.00 v 10010 0.95 v 0.95 v 10001 0.90 v 0.90 v 10000 0.85 v 0.85 v 01111 0.80 v 0.80 v 01110 0.75 v 0.75 v 01101 0.70 v 0.70 v 01100 0.65 v 0.65 v 01011 0.60 v 0.60 v 01010 0.55 v 0.55 v 01001 0.50 v 0.50 v 01000 0.45 v 0.45 v 00111 0.40 v 0.40 v 00110 0.35 v 0.35 v 00101 0.30 v 0.30 v 00100 0.25 v 0.25 v 00011 0.20 v 0.20 v 00010 0.15 v 0.15 v 00001 0.10 v 0.10 v 00000 0.05 v 0.05 v vdd practial vref range note 3.0 v - 5.5 v 50 mv ~1.2 v vdd > 3. 6 v external vref cannot be us ed
000-0046121--106 page 73 of 97 SLG46121 13.3 vref block diagram figure 45. voltage refe rence block diagram cmp0_vref cmp1_vref reg <600:596> reg <611:607> vdd / 3 vdd / 4 *ext_vref_acmp0 (pin4) reg <707> forced bg on 000 001 100 101 110 reg <714> vdd / 2 vdd / 3 vdd / 4 reg <711:709> 1 0 op reg <708> vref out_1 (pin10) pin10_aio_en external vdd 3.0 v - 5.5 v *vdd > 3.6 v external vref cannot be used
000-0046121--106 page 74 of 97 SLG46121 14.0 rc oscillator (rc osc) 14.1 rc oscillator overview the SLG46121 has two internal rc oscillators, one that runs at 25 khz and one that runs at 2 mhz. when using the chip internal rc osc, a choice is available to force power on, meaning that the rc osc will always run, or auto power on, meaning that the rc osc will have an associat ed startup and settling time as sociated with it (offset). figure 46 and figure 47 show maximum power on delay vs. vdd. note: rc osc power setting: "auto power on?. figure 46. maximum power on del ay vs. vdd, rc osc = 2 mhz. figure 47. maximum power on del ay vs. vdd, rc osc = 25 khz.
000-0046121--106 page 75 of 97 SLG46121 the user can select one of these fundamental frequencies for th e rc osc macrocell, or the f undamental frequency can also come from an external clock input (pin 12). there are two divid er stages that allow the user flexibility for introducing clock signals on various connection matrix input lines. the first stage divid er (also known as the clock pre-divider) allows the selection o f /1, /2, /4 or /8 divide down frequency from the fundamental. there are two second stage divider controls (out0 and out1). each has its own input of one frequency from the first stage divider , and outputs two different frequencies on connection matrix in put lines <30>, and <31>. see figure 48 below for details of the frequencies for e ach of these two con nection matrix inputs. if pwr down input of oscillator is low, the oscillator will be turned on. if pwr down input of oscillator is high the oscillat or will be turned off. the pwr down signal has the highest priorit y. 14.2 rc osc bl ock diagram figure 48. rc osc block diagram internal rco reg <536> 0: 25 khz 1: 2 mhz / 2 / 3 / 4 / 8 / 12 / 24 / 64 to connection matrix input <30> reg <541:539> div /1/2/4/8 reg <538:537> clock pre- divider control second stage divider pin 12 ext. clock ext. clk sel reg <545> 0 1 reg <544:542> to connection matrix input <31> from connection matrix output <59> pwr down out0 out1
000-0046121--106 page 76 of 97 SLG46121 15.0 additional logic functions the SLG46121 has one additional logic function that is connecte d directly to the connection ma trix inputs and outputs. there i s one inverter which can switch t he polarity of any connection ma trix signal. 15.1 inv_0 gate figure 49. inv_0 gate inv_0 gate from connection matrix output <15> to connection matrix input <37>
000-0046121--106 page 77 of 97 SLG46121 16.0 power on reset (por) the SLG46121 has a power-on reset (por) macrocell to ensure cor rect device initialization and operation of all macrocells in the device. the purpose of the por circuit is to have consisten t behavior and predictable results when the vdd power is first ramping to the device, and also while the vdd is falling during power-down. to accomplish this goal, the por drives a defined sequence of internal events that trigger changes to the states of different macrocells inside th e device, and finally to the s tate of the i/o pins. this application note is created to explain the w hole process of por operation and greenpak chip behavior during the time while it is power ing up and powering down. 16.1 general operation the SLG46121 is guaranteed to be powered down and nonoperationa l when the vdd voltage (voltage on pin1) is less than 0.6v, but not less than -0.6v. another essential condition for the ch ip to be powered down is that no voltage higher (see note 1) th an the vdd voltage is applied to any other pin. for example, if vd d voltage is 0.3v, applying a voltage higher than 0.3v to any o ther pin is incorrect, and can lead t o incorrect or unexpected devic e behavior. note 1. there is a 0.6v margin due to forw ard drop voltage of t he esd protection diodes. to start the por sequence in the SLG46121, the voltage applied on the vdd should be higher than the power_on threshold (see note 2). the full operationa l vdd range for the SLG46121 i s 1.71 v C 5.5 v (1.8 v 10% - 5 v 10%). this means that the vdd voltage must ramp up to the operational voltage value, but the por sequence will start earlier, as soon as the vdd voltage rises to the power_on threshold. after the por sequence has sta rted, the SLG46121 will have a typical period of time to go through all the steps in the s equence (noted in the datasheet f or that device), and will be r eady and completely operational a fter the por sequence is complete. note 2. the power_on threshold can vary by pvt, but typically it is 1.6 v. to power down the chip the vdd voltage should be lower than the operational and to guarantee that chip is powered down it should be less than 0.6 v. all pins are in high impedance st ate when the chip is powered d own and while the por sequence is taking place. the last step in the por sequence releases the i/o structures from the high i mpedance state, at which time the device is operational. the pi n configuration at this point in time is defined by the design pr ogrammed into the chip. also as it was mentioned before the vol tage on pins cant be bigger than t he vdd, this rule also applies to the case when the chip is powered on. note that vdd2 has no influence on por sequence, all internal m acrocells are powered from vdd. it means, vdd2 can be switched on/off while vdd is o n. if volt age on vdd2 appears aft er the por sequence, pins 8, 9 , 10, 12 become available when vdd2 reaches 0.6 v. for proper power up sequence, mak e sure vdd2 will not exceed vd d at any point during startup. for normal operation vdd should not be switched off while vdd2 is on, due to vdd2vdd,see sect ion 5.0 electrical specifica- tions.
000-0046121--106 page 78 of 97 SLG46121 16.2 por sequence the por system generat es a sequence of signa ls that enable cert ain macrocells. the sequence is shown in figure 50 as can be seen from figure 50 after the vdd has start ramping up and crosses the power_on th reshold, first, the on-chip nvm memory is reset. next the chip reads the data from nvm, and tra nsfers this information to sram registers that serve to configu re each macrocell, and the connection matrix which routes signals between macrocells. the third stage causes the reset of the inp ut pins, and then to enable them. after that, the luts are reset a nd become active. after luts the delay cells, rc osc, dffs, latches and pipe delay are initialized. only after all macrocel ls are initialized internal por s ignal (por macrocell output) g oes from low to high. the last portion of the device to be initiali zed are the output pins, which transition from high impedience to active at this point. the typical time that takes to complete the por sequence varies by device type in the greenpak family. it also depends on many environmental factors, such as: slew rate, vdd value, temperatu re and even will vary from chip to chip (process influence). figure 50. por sequence vdd por_nvm (reset for nvm) nvm_ready_out por_gpi (reset for input enable) por_lut (reset for lut output) por_core (reset for dly/rc osc/dff /latch/pipe dly/other macrocells por_out (generate low to high to matrix) por_gpo (reset for output enable) t t t t t t t t tsu
000-0046121--106 page 79 of 97 SLG46121 16.3 macrocells output states during por sequence to have a full picture of SLG46121 operation during powering an d por sequence, review the overview the macrocell output states during the por sequence ( figure 51 describes the output signals states). first, before the nvm has been res et, all macrocells have their output set to logic low (exc ept the output pins which are in h igh impedance state). before the nv m is ready, all macrocell output s are unpredictable (except the output pins). on the next step, some of the macrocells start ini tialization: input pins output state becomes low; luts also output low. only p dly macrocell configured as edge detector becomes active at this time. after that input pins are enabled. next, only luts are configured. ne xt, all other macrocells are initialized. after macrocells are init ialized, internal por matrix signa l switches from low to high. the last are output pins that become active and determined by the i nput signals. figure 51. internal macrocell states during por sequence unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable vdd input pin_out to matrix lut_out to matrix programmable delay_out to matrix prog. edge_detector_out to matrix dff/latch_out to matrix delay_out to matrix por_out to matrix ext. gpo vdd_out to matrix determined by input signals determined by input signals starts to detect input edges determined by input signals determined by input signals determined by input signals starts to detect input edges determined by input signals determined by external signal guaranteed high before por_gpi determined by input signals out = in without delay determined by initial state determined by input signals out = in without delay tri-state t t t t t t t t t t
000-0046121--106 page 80 of 97 SLG46121 17.0 appendix a - SLG46121 register definition register bit address signal function register bit definition reg<5:0> matrix out: pin3 digital output source reg<11:6> matrix out: pin4 digital output source reg<17:12> matrix out: pin 5 digital output source reg<23:18> matrix out: pin 6 digital output source reg<29:24> matrix out: output enable of pin6 reg<35:30> matrix out: in0 of lu t2_0 or clock input of dff0 reg<41:36> matrix out: in1 of lut2_0 or data input of dff0 reg<47:42> matrix out: in0 of lu t2_1 or clock input of dff1 reg<53:48> matrix out: in1 of lut2_1 or data input of dff1 reg<59:54> matrix out: in0 of lu t2_2 or clock input of dff2 reg<65:60> matrix out: in1 of lut2_2 1 or data input of dff2 reg<71:66> matrix out: in0 of lu t2_3 or clock input of dff3 reg<77:72> matrix out: in1 of lut2_3 1 or data input of dff3 reg<83:78> matrix out: in0 of lut2_4 reg<89:84> matrix out: in1 of lut2_4 reg<95:90> matrix out: in0 of inverter inv_0 reg<101:96> matrix out: pin12 digital output source reg<107:102> matrix out: in0 of lu t3_0 or clock input of dff4 reg<113:108> matrix out: in1 of lut3_0 or data input of dff4 reg<119:114> matrix out: in2 of lut3_0 or resetb input of dff4 reg<125:120> matrix out: in0 of lu t3_1 or clock input of dff5 reg<131:126> matrix out: in1 of lut3_1 or data input of dff5 reg<137:132> matrix out: in2 of lu t3_1 or resetb(setb) of dff5 reg<143:138> matrix out: in0 of lu t3_2 or clock input of dff6 reg<149:144> matrix out: in1 of lut3_2 or data input of dff6 reg<155:150> matrix out: in2 of lu t3_2 or resetb input of dff6 reg<161:156> matrix out: in0 of lu t3_3 or clock input of dff7 reg<167:162> matrix out: in1 of lut3_3 or data input of dff7 reg<173:168> matrix out: in2 of lu t3_3 or resetb(setb) of dff7 reg<179:174> matrix out: in0 of lut3_4 reg<185:180> matrix out: in1 of lut3_4 reg<191:186> matrix out: in2 of lut3_4 reg<197:192> matrix out: in0 of lut3_5 reg<203:198> matrix out: in1 of lut3_5 reg<209:204> matrix out: in2 of lut3_5 reg<215:210> matrix out: in0 of lut3_6 reg<221:216> matrix out: in1 of lut3_6 reg<227:222> matrix out: in2 of lut3_6 reg<233:228> matrix out: in0 of lut3_7 reg<239:234> matrix out: in1 of lut3_7 reg<245:240> matrix out: in2 of lut3_7
000-0046121--106 page 81 of 97 SLG46121 reg<251:246> matrix out: in0 of lu t3_8 or input of pipe delay reg<257:252> matrix out: in1 of lut3_8 or resetb of pipe delay reg<263:258> matrix out: in2 of lut3_8 or clock of pipe delay reg<269:264> matrix out: in0 of lut4_0 or input for delay2(couter2) external clock reg<275:270> matrix out: in1 of lut4_0 or input for delay2 da- ta(counter2 reset) reg<281:276> matrix out: in2 of lut4_0 reg<287:282> matrix out: in3 of lut4_0 reg<293:288> matrix out: in0 of lut4_1 or input for delay3(couter3) external clock reg<299:294> matrix out: in1 of lut4_1 or input for delay3 da- ta(counter3 reset) reg<305:300> matrix out: in2 of lut4_1 reg<311:306> matrix out: in3 of lut4_1 reg<317:312> matrix out: input for delay 0 data(counter0 external clock) reg<323:318> matrix out: input for delay1(counter1) external clo ck reg<329:324> matrix out: input for delay1 data(counter1 reset) reg<335:330> matrix out: not used reg<341:336> matrix out: pdb(power down) for acmp0 reg<347:342> matrix out: pdb(power down) for acmp1 reg<353:348> matrix out: input for programmable delay (deglitch filter input) reg<359:354> matrix out: power down for osc (1: power down) reg<365:360> matrix out: pin8 digital output source reg<371:366> matrix out: pin9 digital output source reg<377:372> matrix out: pin 10 digital output source reg<383:378> matrix out: output enable of pin10 reg<389:384> reserved reg<395:390> reserved lut2_0 or dff0 reg<399:396> lut2_0 data or the following reg<396> dff0 or latch select 0: dff function 1: latch function reg<397> dff0 output select 0: q output 1: nq output reg<398> dff0 initial polarity select 0: low 1: high lut2_1 or dff1 reg<403:400> lut2_1 data or the following 0: dff function 1: latch function reg<400> dff1 or latch select 0: dff function 1: latch function reg<401> dff1 output select 0: q output 1: nq output register bit address signal function register bit definition
000-0046121--106 page 82 of 97 SLG46121 reg<402> dff1 initial polarity select 0: low 1: high lut2_2 or dff2 reg<407:404> lut2_2 data or the following reg<404> dff2 or latch select 0: dff function 1: latch function reg<405> dff2 output select 0: q output 1: nq output reg<406> dff2 initial polarity select 0: low 1: high lut2_3 or dff3 reg<411:408> lut2_3 dat a or the following reg<408> dff3 or latch select 0: dff function 1: latch function reg<409> dff3 output select 0: q output 1: nq output reg<410> dff3 initial polarity select 0: low 1: high lut2_4 reg<415:412> lut2_4 data reg<419:416> reserved lut2/dff select reg<420> lut2_0 or dff0 select 0: lut2_0 1: dff0 reg<421> lut2_1 or dff1 select 0: lut2_1 1: dff1 reg<422> lut2_2 or dff2 select 0: lut2_2 1: dff2 reg<423> lut2_3 or dff3 select 0: lut2_3 1: dff3 lut3_0 or dff4 reg<431:424> lut3_0 data or the following reg<424> dff4 or latch select 0: dff function 1: latch function reg<425> dff4 output select 0: q output 1: nq output reg<426> dff4 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<427> dff4 initial polarity select 0: low 1: high lut3_1 or dff5 reg<439:432> lut3_1 data or the following reg<432> dff5 or latch select 0: dff function 1: latch function reg<433> dff5 output select 0: q output 1: nq output reg<434> dff5 rstb/setb select 0: resetb from matrix output 1: setb from matrix output register bit address signal function register bit definition
000-0046121--106 page 83 of 97 SLG46121 reg<435> dff5 initial polarity select 0: low 1: high lut3_2 or dff6 reg<447:440> lut3_2 data or the following reg<440> dff6 or latch select 0: dff function 1: latch function reg<441> dff6 output select 0: q output 1: nq output reg<442> dff6 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<443> dff6 initial polarity select 0: low 1: high lut3_3 or dff7 reg<455:448> lut3_3 data or the following reg<448> dff7 or latch select 0: dff function 1: latch function reg<449> dff7 output select 0: q output 1: nq output reg<450> dff7 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<451> dff7 initial polarity select 0: low 1: high lut3_4 reg<463:456> lut3_4 data lut3_5 reg<471:464> lut3_5 data lut3_6 reg<479:472> lut3_6 data lut3_7 reg<487:480> lut3_7 data lut3_8 or pip number select reg<495:488> reg<490:488>: out0 sele ct data (pipe number) reg<493:491>: out1 sele ct data (pipe number) reg<495:494>: unused if pi pe delay selected unused lut3/dff select reg<496> lut3_0 or dff4 select 0: lut3_0 1: dff4 reg<497> lut3_1 or dff5 select 0: lut3_1 1: dff5 reg<498> lut3_2 or dff6 select 0: lut3_3 1: dff6 reg<499> lut3_3 or dff7 select 0: lut3_4 1: dff7 reg<500> lut3_8 or pipe delay output select 0: lut3_8 1: pipe delay lut4_0 or counter/delay2 reg<516:501> lut4_0 data data or the following register bit address signal function register bit definition
000-0046121--106 page 84 of 97 SLG46121 reg<501> counter/delay 2 mode selection 0: delay mode 1: counter mode reg<504:502> counter/delay 2 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter1 overflow reg<512:505> counter/delay2 contro l data 1 - 256 (delay time = ( counter control data +2) /freq ) reg <514:513> delay2 mode select or asynchronous counter reset 00: on both falling and rising edges(for delay & count- er reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falli ng or rising edges / high level reset for counter mode reg<517> lut4_0 or counter2 select 0: lut4_0 1: counter2 lut4_1 or counter/delay3 reg<533:518> lut4_1 data or the following reg<518> counter/delay 3 mode selection 0: de lay mode 1: counter mode reg<521:519> counter/delay 3 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter1 overflow reg<529:522> counter/delay3 contro l data 1 - 256 (delay time = (counter control data +2) /freq ) reg<531:530> delay3 mode select or asynchronous counter reset 00: on both falling and rising edges(for delay & count- er reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either fa lling or rising edges reg<534> lut4_1 or counter3 select 0: lut4_1 1: counter3 rc osc reg<535> force rc oscillator on 0: auto power on 1: force power on reg<536> rc oscillato r frequency control 0: 25 khz 1: 2 mhz reg<538:537> osc clock pre-divider 00:div1 01:div2 10: div4 11: div8 register bit address signal function register bit definition
000-0046121--106 page 85 of 97 SLG46121 reg<541:539> internal oscillator frequency divider control 0 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 reg<544:542> internal oscillator frequency divider control 1 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 reg<545> external clock source select 0: internal oscillator 1: external clock from pin12 reg<546> manufacturing test mode reg<547> reserved counter/delay 0 reg<548> counter/delay 0 mode selection 0: delay mode 1: counter mode reg<551:549> counter/delay0 clock source s elect (external clock is only for counter mode) 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter3 overflow reg<565:552> counter0 control data/delay0 time control 1-16384: (delay time = (coun ter control data +2) /freq) reg<567:566> delay0 mode select o r asynchronous counter reset 00: on both falling and rising edges 01: on falling edge only 10: on rising edge only 11: no delay on either fa lling or rising edges counter/delay 1 reg<568> counter/delay 1 mode selection 0: delay mode 1: counter mode reg<571:569> counter/delay 1 clock source select 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: external clock 110: external clock 111: counter0 overflow reg<579:572> counter1 control data /delay1 time control 1-256: (de lay time = (counter co ntrol data +2) /freq) register bit address signal function register bit definition
000-0046121--106 page 86 of 97 SLG46121 reg<581:580> delay1 mode select o r asynchronous counter reset 00: on both falling and rising edges(for delay & count- er reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falli ng or rising edges / high level reset for counter mode reg<595:582> reserved acmp0 reg<600:596> acmp0 in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin4) reg<602:601> acmp0 hysteresis enable 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) reg<604:603> acmp0 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg<605> acmp0 low bandwidth ( typ: max.1 mhz) enable. 0: off 1: on reg<606> acmp0 positive input source select pin3 and vdd 0: pin3 1: vdd acmp1 reg<611:607> acmp1 in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: ext_vref(pin4) reg<613:612> acmp1 hysteresis enable 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) register bit address signal function register bit definition
000-0046121--106 page 87 of 97 SLG46121 reg<615:614> acmp1 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x reg<616> acmp1 100ua c urrent source option 0: disable 1: enable reg<617> acmp1 low bandwidth (typ: max.1mhz) enable. 0: off 1: on reg<618> acmp1 positive input source select pin6 and pin3 0: pin3 1: pin6 reg<622:619> reserved reserved pin 2 reg<624:623> pin2 mode control 00: digital input wit hout schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved reg<626:625 > pin2 pull down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m pin 3 reg<629:627 > pin3 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain reg<631:630 > pin3 pull up/down resistor val ue selection 00: floating 01: 10k 10: 100k 11: 1m reg<632> pin3 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<633> pin3 driver strength selection 0: 1x 1: 2x pin 4 reg<636:634> pin4 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain reg<638:637> pin4 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m reg<639> pin4 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable register bit address signal function register bit definition
000-0046121--106 page 88 of 97 SLG46121 reg<640> pin4 driver strength selection 0: 1x 1: 2x pin 5 reg<643:641> pin5 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos reg<645:644> pin5 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m reg<646> pin5 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<647> pin5 driver strength selection 0: 1x 1: 2x pin 6 reg<649:648> pin6 mode c ontrol (sig_pin6_oe =0) 00: digital input wit hout schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input / output reg<651:650> pin6 mode c ontrol (sig_pin6_oe =1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11:open drain nmos 2x reg<653:652> pin6 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m reg<654> pin6 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable pin8 reg<657:655> pin8 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos reg<659:658> pin8 pull up/down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m reg<660> pin8 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<661> pin8 driver strength selection 0: 1x 1: 2x register bit address signal function register bit definition
000-0046121--106 page 89 of 97 SLG46121 pin 9 reg<664:662> pin9 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos reg<666:665> pin9 pull down resistor value selection 00: floating 01: 10k 10: 100k 11: 1m reg<667> pin9 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<668> pin9 driver strength selection 0: 1x 1: 2x pin 10 reg<670:669> pin10 mode control (sig_pin10_oe =0) 00: digital input wit hout schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input / output reg<672:671> pin10 mode control (sig_pin10_oe =1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11:open drain nmos 2x reg<674:673> pin10 pull up/dow n resistor value selection 00: floating 01: 10k 10: 100k 11: 1m reg<675> pin10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reserved reg<678:676> reserved reg<680:679> reserved reg<681> reserved reg<682> reserved pin 12 reg<685:683> pin12 mode control 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain reg<687:686> pin12 pull up/dow n resistor value selection 00: floating 01: 10k 10: 100k 11: 1m reg<688> pin12 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable register bit address signal function register bit definition
000-0046121--106 page 90 of 97 SLG46121 reg<689> pin12 driver strength selection 0: 1x 1: 2x reg<690> pipe delay out1 polarity select bit 0: non-inverted 1: inverted reg<698:691> 8-bit pattern id reg<699> filter0 output polarity select 0: non-inverting 1: inverting reg<701:700> reserved reserved reg<702> gpio quick charge enable 0: disable 1: enable reg<706:703> reserved reserved reg<707> force bandgap on 0: auto-mode 1: enable reg<708> vref1 output active buffer control 0: disabled 1: enabled reg<711:709> vref1 output source select 000: acmp0 reference voltage 001: acmp1 reference voltage 100: vdd/2 101: vdd/3 110: vdd/4 reg<712> nvm dat a read disable 0: disable (read enable) 1: enable (read disable) reg<713> nvm power down (or nv m data programming disable) 0: none (or programming enable) 1: power down (or pr ogramming disable) reg<714> power divider power 0: power down 1: power on reg<715> por auto power detect 0: enable 1: disable reg<716> charge pump for analog macrocell enable (when vdd <=2.7v turn on) 0: disable (automat ic on/off control) 1: enable (always on) reg<717> vdd bypass enable 0: regulator auto on 1: regualtor off (vdd bypass) reg<718> pin2 edge detect mode 0: rising edge 1: falling edge reg<719> bypass the pin2 0: pin2 edge active 1: pin2 high active reg<720> pin2 reset enable 0: disable 1: enable reg<721> reserved reserved reg<727:722> reserved reserved reg<735:728> reserved reserved reg<741:736> reserved reserved reg<743:742> delay value select for pro grammable delay & edge de- tector (vdd = 3.3v, typical condition) 00: 163 ns 01: 305 ns 10: 446 ns 11: 588 ns reg<745:744> select the edge mode of programmable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay register bit address signal function register bit definition
000-0046121--106 page 91 of 97 SLG46121 reg<746> programmable delay or filter output select 0: programmable delay output 1: filter output reg<751:747> reserved reserved reg<757:752> reserved reserved reg<758> reserved reserved reg<759> reserved reserved reg<767:760> reserved reserved register bit address signal function register bit definition
000-0046121--106 page 92 of 97 SLG46121 18.0 package top marking system definition p p a part code + assembly code pin 1 identifier wwr date code + revision code nn serial number code
000-0046121--106 page 93 of 97 SLG46121 19.0 package drawing and dimensions 12 lead stqfn fca pack age 1.6 x 1.6 mm
000-0046121--106 page 94 of 97 SLG46121 20.0 tape and reel specifications 20.1 carrier tape drawing and dimensions package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] stqfn 12l fca 0.4p green 10 1.6x1.6x0.55 3000 3000 178/60 100 400 100 400 8 4 package type pocket btm length [mm] pocket btm width [mm] pocket depth [mm] index hole pitch [mm] pocket pitch [mm] index hole diameter [mm] index hole to tape edge [mm] index hole to pocket center [mm] tape width [mm] a0 b0 k0 p0 p1 d0 e f w stqfn 12l fca 0.4p green 1.9 1.9 0.8 4 4 1.5 1.75 3.5 8
000-0046121--106 page 95 of 97 SLG46121 21.0 recommended land pattern 22.0 recommended reflow soldering profile please see ipc/jedec j-std-020: l atest revision for reflow prof ile based on package volume of 1.408 mm 3 (nominal). more information can be f ound at www.jedec.org. units: ? m
000-0046121--106 page 96 of 97 SLG46121 23.0 revision history date version change 10/11/2017 1.06 updated electrical spec fixed typos updated por sequence 5/7/2017 1.05 fixed typos updated silego w ebsite & support updated section programmable delay / edge detector updated electrical spec 5/30/2016 1.04 updat ed programmable delay information 2/1/2016 1.03 updated section power on reset 1/29/2016 1.02 updated silego w ebsite & support fixed typos 12/29/2015 1.01 updated electrical spec 12/9/2015 1.00 production release 12/7/2015 0.52 updated front page 11/19/2015 0.51 added vdd2 information to por section updated pin description updated absolute maximum conditions 11/04/2015 0.50 preliminary release 10/28/2015 0.15 updated abso lute maximum conditions 10/20/2015 0.14 fixed typos 9/16/2015 0.13 added vdd2 tables added vhys, rpup, rpdwn, ponthr, poffthr added el. spec table for vdd = 1.8 v 8/25/2015 0.12 updated references to vdd and vdd2 fixed typos updated front page, sections 1, 5, 6, 7, 8 , 9, 10, 12. 7/21/2015 0.11 updated elec trical characteristics 6/24/2015 0.1 initial release
000-0046121--106 page 97 of 97 SLG46121 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding si lego green products, please vi sit our website. our green product lines feature: greenpak: programmable mixed signal matrix products greenfet1 / greenfet3 / hfet1: mos fet drivers and ultra-small, low rdson load switches greenclk1 / greenclk2 / greenclk 3: crystal replacement technolo gy products are also available for purchase directly from silego a t the silego on line store at http://www.silego.com /buy/ . silego technical support datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications questions and supp ort please send e-mail requests to greenpak@silego.com users of silego products can rec eive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for support. local sales offices ar e also available to help customers. more information regarding your lo cal representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted d irectly via e-mail at info@silego.com or user submission form, l ocated at the f ollowing url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminar s and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed an d qualified for the consumer m arket. applications or uses as critical components in life support devices or systems are n ot authorized. silego technolog y does not assume any liability arising out of such applica- tions or uses of its products. silego technology reserves the r ight to improve product design , functions and reliability without noti

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